| busy | va1_strobe | [Port] |
| clk | va1_strobe | [Port] |
| cnt_i | behaviour | [Signal] |
| div | va1_strobe | [Port] |
| div_cnt_i | behaviour | [Signal] |
| div_i | behaviour | [Signal] |
| div_ii | behaviour | [Signal] |
| dreset | va1_strobe | [Port] |
| first | va1_strobe | [Port] |
| first_i | behaviour | [Signal] |
| first_ii | behaviour | [Signal] |
| fsm(clk, rstb) | behaviour | [Process] |
| ieee | va1_strobe | [Library] |
| last | va1_strobe | [Port] |
| last_i | behaviour | [Signal] |
| last_ii | behaviour | [Signal] |
| numeric_std | va1_strobe | [Package] |
| phase | va1_strobe | [Port] |
| phase_cnt_i | behaviour | [Signal] |
| phase_ii | behaviour | [Signal] |
| RESET_LEN | behaviour | [Constant] |
| rst_cnt_i | behaviour | [Signal] |
| rstb | va1_strobe | [Port] |
| shift_clk | va1_strobe | [Port] |
| shift_clk_i | behaviour | [Signal] |
| shift_down_i | behaviour | [Signal] |
| shift_en_i | behaviour | [Signal] |
| shift_gen(clk, rstb) | behaviour | [Process] |
| shift_in | va1_strobe | [Port] |
| shift_out_i | behaviour | [Signal] |
| shift_up_i | behaviour | [Signal] |
| start | va1_strobe | [Port] |
| state_i | behaviour | [Signal] |
| state_t | behaviour | [Type] |
| std_logic_1164 | va1_strobe | [Package] |
| take_i | behaviour | [Signal] |
1.6.2-20100208