behaviour Architecture Reference

Inheritance diagram for behaviour:

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Collaboration diagram for behaviour:

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List of all members.

Processes
fsm	( clk , rstb )
shift_gen	( clk , rstb )
Constants
RESET_LEN	integer := 4
Types
state_t	( idle , delay , stay_on_strip , wait_shift_down , clocking , wait_reset , reset , wait_shift_reset , shift_reset , setup )
Signals
state_i	state_t
div_i	integer range 0 to 2 **8
div_ii	integer range 0 to 2 **8
div_cnt_i	integer range 0 to 2 **8
phase_ii	integer range 0 to 2 **8
cnt_i	integer range 0 to 2 **8
first_i	integer range 0 to 2 **8
first_ii	integer range 0 to 2 **8
last_i	integer range 0 to 2 **8
last_ii	integer range 0 to 2 **8
rst_cnt_i	integer range 0 to 2 **8
phase_cnt_i	integer range 0 to 2 **8
shift_en_i	std_logic
shift_up_i	std_logic
shift_down_i	std_logic
shift_out_i	std_logic
shift_clk_i	std_logic
take_i	std_logic

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Detailed Description

Architecture of VA1 strobe generator.

The strobe generator is initialised by the start signal. It will then start strobing the VA1s after phase clock cycles. Note that there's an implicit delay of 3 clock cycles (= 75ns) from the reception of the start signal.

Note, that the rest of the design may implicitly introduce an additinal delay on the start signal. This must be factored in when tunning the setting of phase.

The period of the strobe is set by the input div, so tha the period is equal to .

The range strips (and consequently the number of strobes) is set by the inputs first and last. If the value of first is changed, then the architecture will set-up the VA1 pointer to that value. That means sending a single shift_clk pulse together with a shift_in pulse (which resets the cursor to the start of the VA1) , and then send first shift_clk pulses.

When start signal arrives, the architecture will send (last - first) strobes, then send a digital reset (dreset) strobe, and then do a setup as outlined above.

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Member Function Documentation

[Process]

fsm		( clk ,
		rstb )

[Process]

shift_gen		( clk ,
		rstb )

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Member Data Documentation

cnt_i integer range 0 to 2 **8 [Signal]

div_cnt_i integer range 0 to 2 **8 [Signal]

div_i integer range 0 to 2 **8 [Signal]

div_ii integer range 0 to 2 **8 [Signal]

first_i integer range 0 to 2 **8 [Signal]

first_ii integer range 0 to 2 **8 [Signal]

last_i integer range 0 to 2 **8 [Signal]

last_ii integer range 0 to 2 **8 [Signal]

phase_cnt_i integer range 0 to 2 **8 [Signal]

phase_ii integer range 0 to 2 **8 [Signal]

RESET_LEN integer := 4 [Constant]

rst_cnt_i integer range 0 to 2 **8 [Signal]

shift_clk_i std_logic [Signal]

shift_down_i std_logic [Signal]

shift_en_i std_logic [Signal]

shift_out_i std_logic [Signal]

shift_up_i std_logic [Signal]

state_i state_t [Signal]

state_t ( idle , delay , stay_on_strip , wait_shift_down , clocking , wait_reset , reset , wait_shift_reset , shift_reset , setup ) [Type]

take_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• bc/fmdd/va1_strobe/va1_strobe.vhd