va1_readout Entity Reference

Inheritance diagram for va1_readout:

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Collaboration diagram for va1_readout:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
Generics
DRESET_LENGTH	integer := 4
L1_LENGTH	integer := 8
SIZE	integer := 128
Ports
clk	in std_logic
rstb	in std_logic
clear	in std_logic
va_clk	in std_logic
first	in std_logic_vector ( 7 downto 0 )
last	in std_logic_vector ( 7 downto 0 )
start	in std_logic
busy	out std_logic
l1	out std_logic
shift_clk	out std_logic
shift_in	out std_logic
digital_reset	out std_logic

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Member Data Documentation

busy out std_logic [Port]

clear in std_logic [Port]

clk in std_logic [Port]

digital_reset out std_logic [Port]

DRESET_LENGTH integer := 4 [Generic]

first in std_logic_vector ( 7 downto 0 ) [Port]

ieee library [Library]

l1 out std_logic [Port]

L1_LENGTH integer := 8 [Generic]

last in std_logic_vector ( 7 downto 0 ) [Port]

numeric_std package [Package]

rstb in std_logic [Port]

shift_clk out std_logic [Port]

shift_in out std_logic [Port]

SIZE integer := 128 [Generic]

start in std_logic [Port]

std_logic_1164 package [Package]

va_clk in std_logic [Port]

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The documentation for this class was generated from the following file:

• bc/fmdd/va1_readout/va1_readout.vhd