rtl Architecture Reference

Inheritance diagram for rtl:

[legend]

Collaboration diagram for rtl:

[legend]

List of all members.

Processes
delay_clk	( clk , rstb )
PROCESS_0	( clk , rstb , clear )
Types
state_t	( idle , clocking_va , clocking_wait_va_clk , clocking_wait_falling_edge , clocking_wait_rissing_edge , reset , setup , setup_check_va_clk , setup_wait_va_clk , setup_wait_next_va_clk , setup_2_min , keep_l1 )
Signals
va_clk_i	std_logic
va_clk_en_i	std_logic
state_i	state_t
last_i	integer range 0 to SIZE := SIZE
first_i	integer range 0 to SIZE := 0
shift_cnt_i	integer range 0 to SIZE
reset_cnt_i	integer range 0 to 15
l1_cnt_i	integer range 0 to L1_LENGTH +10

---

Member Function Documentation

[Process]

delay_clk		( clk ,
		rstb )

[Process]

PROCESS_0		( clk ,
		rstb ,
		clear )

---

Member Data Documentation

first_i integer range 0 to SIZE := 0 [Signal]

l1_cnt_i integer range 0 to L1_LENGTH +10 [Signal]

last_i integer range 0 to SIZE := SIZE [Signal]

reset_cnt_i integer range 0 to 15 [Signal]

shift_cnt_i integer range 0 to SIZE [Signal]

state_i state_t [Signal]

state_t ( idle , clocking_va , clocking_wait_va_clk , clocking_wait_falling_edge , clocking_wait_rissing_edge , reset , setup , setup_check_va_clk , setup_wait_va_clk , setup_wait_next_va_clk , setup_2_min , keep_l1 ) [Type]

va_clk_en_i std_logic [Signal]

va_clk_i std_logic [Signal]

---

The documentation for this class was generated from the following file:

• bc/fmdd/va1_readout/va1_readout.vhd