busy | va1_readout | [Port] |
clear | va1_readout | [Port] |
clk | va1_readout | [Port] |
delay_clk(clk, rstb) | rtl | [Process] |
digital_reset | va1_readout | [Port] |
DRESET_LENGTH | va1_readout | [Generic] |
first | va1_readout | [Port] |
first_i | rtl | [Signal] |
ieee | va1_readout | [Library] |
l1 | va1_readout | [Port] |
l1_cnt_i | rtl | [Signal] |
L1_LENGTH | va1_readout | [Generic] |
last | va1_readout | [Port] |
last_i | rtl | [Signal] |
numeric_std | va1_readout | [Package] |
PROCESS_0(clk, rstb, clear) | rtl | [Process] |
reset_cnt_i | rtl | [Signal] |
rstb | va1_readout | [Port] |
shift_clk | va1_readout | [Port] |
shift_cnt_i | rtl | [Signal] |
shift_in | va1_readout | [Port] |
SIZE | va1_readout | [Generic] |
start | va1_readout | [Port] |
state_i | rtl | [Signal] |
state_t | rtl | [Type] |
std_logic_1164 | va1_readout | [Package] |
va_clk | va1_readout | [Port] |
va_clk_en_i | rtl | [Signal] |
va_clk_i | rtl | [Signal] |