rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
nedge_detect	( clk , rstb )
ram	( clk , rstb )
Types
ram_t	array ( 511 downto 0 ) of std_logic_vector ( 39 downto 0 )
Signals
ram_in_i	std_logic_vector ( 39 downto 0 )
sclk_edge_i	std_logic
tsm_acqon_i	std_logic
mem_wren_i	std_logic
mem_wren_ii	std_logic
mem_wraddr_i	std_logic_vector ( 8 downto 0 )
mem_rdaddr_i	std_logic_vector ( 8 downto 0 )
mem_wraddr_ii	std_logic_vector ( 8 downto 0 )
mem_rdaddr_ii	std_logic_vector ( 8 downto 0 )
sclk_i	std_logic
sclk_ii	std_logic
ram_i	ram_t := ( others = > ( others = > ' 0 ' ) )
Component Instantiations
mem_writer	mem_wr <Entity mem_wr>
mem_reader	mem_rdo <Entity mem_rdo>

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Member Function Documentation

[Process]

nedge_detect		( clk ,
		rstb )

[Process]

ram		( clk ,
		rstb )

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Member Data Documentation

mem_rdaddr_i std_logic_vector ( 8 downto 0 ) [Signal]

mem_rdaddr_ii std_logic_vector ( 8 downto 0 ) [Signal]

mem_reader mem_rdo [Component Instantiation]

mem_wraddr_i std_logic_vector ( 8 downto 0 ) [Signal]

mem_wraddr_ii std_logic_vector ( 8 downto 0 ) [Signal]

mem_wren_i std_logic [Signal]

mem_wren_ii std_logic [Signal]

mem_writer mem_wr [Component Instantiation]

ram_i ram_t := ( others = > ( others = > ' 0 ' ) ) [Signal]

ram_in_i std_logic_vector ( 39 downto 0 ) [Signal]

ram_t array ( 511 downto 0 ) of std_logic_vector ( 39 downto 0 ) [Type]

sclk_edge_i std_logic [Signal]

sclk_i std_logic [Signal]

sclk_ii std_logic [Signal]

tsm_acqon_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• bc/bc_core/tsm_man/tsm_man.vhd