mem_wr Entity Reference

Inheritance diagram for mem_wr:

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Collaboration diagram for mem_wr:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
Ports
clk	in std_logic
rstb	in std_logic
sclk_edge	in std_logic
missed_sclk	in std_logic
st_tsm	in std_logic
us_ratio	in std_logic_vector ( 15 downto 0 )
tsm_word	in std_logic_vector ( 8 downto 0 )
mem_wren	out std_logic
mem_wraddr	out std_logic_vector ( 8 downto 0 )
tsm_acqon	out std_logic
tsm_isol	out std_logic

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Member Data Documentation

clk in std_logic [Port]

ieee library [Library]

mem_wraddr out std_logic_vector ( 8 downto 0 ) [Port]

mem_wren out std_logic [Port]

missed_sclk in std_logic [Port]

numeric_std package [Package]

rstb in std_logic [Port]

sclk_edge in std_logic [Port]

st_tsm in std_logic [Port]

std_logic_1164 package [Package]

tsm_acqon out std_logic [Port]

tsm_isol out std_logic [Port]

tsm_word in std_logic_vector ( 8 downto 0 ) [Port]

us_ratio in std_logic_vector ( 15 downto 0 ) [Port]

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The documentation for this class was generated from the following file:

• bc/bc_core/tsm_man/mem_wr/mem_wr.vhd