rtl Architecture Reference
Inheritance diagram for rtl:
Collaboration diagram for rtl:
Processes | |
| fsm | ( clk , rstb ) |
| count_sclk | ( clk , rstb ) |
| count_add | ( clk , rstb ) |
Types | |
| state_t | ( s0 , s1 , s2 ) |
Signals | |
| st_i | state_t |
| cnt_add_i | unsigned ( 8 downto 0 ) |
| cnt_sclk_i | unsigned ( 15 downto 0 ) |
| mem_wren_i | std_logic |
| clr_cnt_sclk_i | std_logic |
| clr_cnt_add_i | std_logic |
| en_cnt_sclk_i | std_logic |
Member Function Documentation
| count_add | ( clk , | |
| rstb ) |
| count_sclk | ( clk , | |
| rstb ) |
| fsm | ( clk , | |
| rstb ) |
Member Data Documentation
clr_cnt_add_i std_logic [Signal] |
clr_cnt_sclk_i std_logic [Signal] |
cnt_add_i unsigned ( 8 downto 0 ) [Signal] |
cnt_sclk_i unsigned ( 15 downto 0 ) [Signal] |
en_cnt_sclk_i std_logic [Signal] |
mem_wren_i std_logic [Signal] |
state_t ( s0 , s1 , s2 ) [Type] |
The documentation for this class was generated from the following file:
- bc/bc_core/tsm_man/mem_wr/mem_wr.vhd
