rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
next_state	( clk , rstb )
fsm	( st , stcnv , ready , width , en_add , data_rom , error , wait_seq_i , rw_i , start_i , stop_i , data_valid , s , end_seq_i )
counter_rom	( clk , rstb )
counter_regs	( clk , rstb )
Constants
seq_start	unsigned ( 2 downto 0 ) := " 110 "
seq_stop	unsigned ( 2 downto 0 ) := " 001 "
seq_data_wr	unsigned ( 2 downto 0 ) := " 010 "
seq_data_rd	unsigned ( 2 downto 0 ) := " 011 "
seq_end	unsigned ( 2 downto 0 ) := " 101 "
add_rom_i	unsigned ( 9 downto 0 ) := ( others = > ' 0 ' )
add_reg_i	unsigned ( 4 downto 0 ) := to_unsigned ( BASE_ADC , 5 )
vendor	unsigned ( 3 downto 0 ) := " 0101 "
Types
state	( idle , read_rom , load_data , wait_ready , write_regs , inc_cnt_regs , inc_cnt_rom , wait_1 , wait_2 , wait_3 )
Signals
st	state
nx_st	state
start_i	boolean
stop_i	boolean
rw_i	boolean
end_seq_i	boolean
wait_seq_i	boolean
rom_en_i	boolean
load_add_regs_i	std_logic
cnt_en_add_regs_i	std_logic
load_rom_i	std_logic
cnt_en_rom_i	std_logic
instr_i	unsigned ( 2 downto 0 ) := ( others = > ' 0 ' )
Aliases
instr	data_rom ( 10 downto 8 )

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Member Function Documentation

[Process]

counter_regs		( clk ,
		rstb )

[Process]

counter_rom		( clk ,
		rstb )

[Process]

fsm		( st ,
		stcnv ,
		ready ,
		width ,
		en_add ,
		data_rom ,
		error ,
		wait_seq_i ,
		rw_i ,
		start_i ,
		stop_i ,
		data_valid ,
		s ,
		end_seq_i )

[Process]

next_state		( clk ,
		rstb )

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Member Data Documentation

add_reg_i unsigned ( 4 downto 0 ) := to_unsigned ( BASE_ADC , 5 ) [Constant]

add_rom_i unsigned ( 9 downto 0 ) := ( others = > ' 0 ' ) [Constant]

cnt_en_add_regs_i std_logic [Signal]

cnt_en_rom_i std_logic [Signal]

end_seq_i boolean [Signal]

instr data_rom ( 10 downto 8 ) [Alias]

instr_i unsigned ( 2 downto 0 ) := ( others = > ' 0 ' ) [Signal]

load_add_regs_i std_logic [Signal]

load_rom_i std_logic [Signal]

nx_st state [Signal]

rom_en_i boolean [Signal]

rw_i boolean [Signal]

seq_data_rd unsigned ( 2 downto 0 ) := " 011 " [Constant]

seq_data_wr unsigned ( 2 downto 0 ) := " 010 " [Constant]

seq_end unsigned ( 2 downto 0 ) := " 101 " [Constant]

seq_start unsigned ( 2 downto 0 ) := " 110 " [Constant]

seq_stop unsigned ( 2 downto 0 ) := " 001 " [Constant]

st state [Signal]

start_i boolean [Signal]

state ( idle , read_rom , load_data , wait_ready , write_regs , inc_cnt_regs , inc_cnt_rom , wait_1 , wait_2 , wait_3 ) [Type]

stop_i boolean [Signal]

vendor unsigned ( 3 downto 0 ) := " 0101 " [Constant]

wait_seq_i boolean [Signal]

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The documentation for this class was generated from the following file:

• bc/bc_core/interface_adc/sequencer/sequencer.vhd