sequencer Entity Reference

Inheritance diagram for sequencer:

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Collaboration diagram for sequencer:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
register_config	Package <register_config>
Ports
clk	in std_logic
rstb	in std_logic
data_valid	in std_logic
data_rom	in std_logic_vector ( 10 downto 0 )
en_add	in std_logic
error	in std_logic
ready	in std_logic
s	in std_logic
stcnv	in std_logic
width	in std_logic
data	out std_logic_vector ( 7 downto 0 )
address_rom	out std_logic_vector ( 9 downto 0 )
address_regs	out std_logic_vector ( 4 downto 0 )
new_data	out std_logic
rw	out std_logic
start	out std_logic
stop	out std_logic
we_adc	out std_logic
end_seq	out std_logic

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Member Data Documentation

address_regs out std_logic_vector ( 4 downto 0 ) [Port]

address_rom out std_logic_vector ( 9 downto 0 ) [Port]

clk in std_logic [Port]

data out std_logic_vector ( 7 downto 0 ) [Port]

data_rom in std_logic_vector ( 10 downto 0 ) [Port]

data_valid in std_logic [Port]

en_add in std_logic [Port]

end_seq out std_logic [Port]

error in std_logic [Port]

ieee library [Library]

new_data out std_logic [Port]

numeric_std package [Package]

ready in std_logic [Port]

register_config package [Package]

rstb in std_logic [Port]

rw out std_logic [Port]

s in std_logic [Port]

start out std_logic [Port]

stcnv in std_logic [Port]

std_logic_1164 package [Package]

stop out std_logic [Port]

we_adc out std_logic [Port]

width in std_logic [Port]

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The documentation for this class was generated from the following file:

• bc/bc_core/interface_adc/sequencer/sequencer.vhd