rtl Architecture Reference

Inheritance diagram for rtl:

[legend]

Collaboration diagram for rtl:

[legend]

List of all members.

Processes
bit_1	( clk , rstb )
bit_0	( clk , rstb )
execute	( clk , rstb )
exec_out	( clk , rstb )
Signals
fec_add_i	std_logic_vector ( 4 downto 0 )
err0_i	std_logic
err1_i	std_logic
exec_reg1_i	std_logic
exec_reg2_i	std_logic
exec_i	std_logic

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Member Function Documentation

[Process]

bit_0		( clk ,
		rstb )

[Process]

bit_1		( clk ,
		rstb )

[Process]

exec_out		( clk ,
		rstb )

[Process]

execute		( clk ,
		rstb )

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Member Data Documentation

err0_i std_logic [Signal]

err1_i std_logic [Signal]

exec_i std_logic [Signal]

exec_reg1_i std_logic [Signal]

exec_reg2_i std_logic [Signal]

fec_add_i std_logic_vector ( 4 downto 0 ) [Signal]

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The documentation for this class was generated from the following file:

• msmodule/msm_error_module/msm_error_module.vhd