bit_0(clk, rstb) | rtl | [Process] |
bit_1(clk, rstb) | rtl | [Process] |
err0_i | rtl | [Signal] |
err1_i | rtl | [Signal] |
exec_i | rtl | [Signal] |
exec_out(clk, rstb) | rtl | [Process] |
exec_reg1_i | rtl | [Signal] |
exec_reg2_i | rtl | [Signal] |
execute(clk, rstb) | rtl | [Process] |
fec_add_i | rtl | [Signal] |