rtl Architecture Reference
[Model of ALTRO chip]

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
p_exec	( clk2 , rstb )
Signals
x1_i	std_logic
busyb_i	std_logic
w0_i	std_logic
r1_i	std_logic
r2_i	std_logic
ack_i	std_logic
Component Instantiations
i_sync	sync21 <Entity sync21>
	Syncronise exec to clk, and clk2.

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Detailed Description

Execute instructions

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Member Function Documentation

[Process]

p_exec		( clk2 ,
		rstb )

Execute

Parameters:

	clk2	40MHz clock
	rstb	Async. reset

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Member Data Documentation

ack_i std_logic [Signal]

busyb_i std_logic [Signal]

i_sync sync21 [Component Instantiation]

Syncronise exec to clk, and clk2.

r1_i std_logic [Signal]

r2_i std_logic [Signal]

w0_i std_logic [Signal]

x1_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• altro/intexec.vhd