structure Architecture Reference

Inheritance diagram for structure:

[legend]

Collaboration diagram for structure:

[legend]

List of all members.

Components
dffe	<Entity dffe>
and1	<Entity and1>
mux21	<Entity mux21>
nmux21	<Entity nmux21>
bmux21	<Entity bmux21>
flex10ke_asynch_mem	<Entity flex10ke_asynch_mem>
Signals
dataout_reg	std_logic
re_reg	std_logic
we_reg	std_logic
datain_reg	std_logic
we_reg_mux_delayed	std_logic
we_reg_mux	std_logic
waddr_reg	std_logic_vector ( 10 downto 0 )
raddr_reg	std_logic_vector ( 10 downto 0 )
dataout_int	std_logic
re_int	std_logic
we_int	std_logic
datain_int	std_logic
waddr_int	std_logic_vector ( 10 downto 0 )
raddr_int	std_logic_vector ( 10 downto 0 )
dataouten	std_logic
raddren	std_logic
reen	std_logic
datain_clr	std_logic
raddr_clk	std_logic
re_clk	std_logic
raddr_reg_sel	std_logic
write_reg_sel	std_logic
datain_reg_sel	std_logic
re_en_sel	std_logic
re_clk_sel	std_logic
dataout_reg_sel	std_logic
re_reg_sel	std_logic
raddr_en_sel	std_logic
raddr_clk_sel	std_logic
dataout_en_sel	std_logic
raddr_reg_clr	std_logic
waddr_reg_clr	std_logic
datain_reg_clr	std_logic
we_reg_clr	std_logic
dataout_reg_clr	std_logic
re_reg_clr	std_logic
datain_reg_clr_sel	std_logic
waddr_reg_clr_sel	std_logic
we_reg_clr_sel	std_logic
raddr_reg_clr_sel	std_logic
dataout_reg_clr_sel	std_logic
re_reg_clr_sel	std_logic
NC	std_logic := ' 0 '
dataoutreg_clr	std_logic
rereg_clr	std_logic
wereg_clr	std_logic
dinreg_clr	std_logic
waddrreg_clr	std_logic
raddrreg_clr	std_logic
we_pulse	std_logic
valid_addr	std_logic
dataout_tmp	std_logic
raddr_num	integer
waddr_reg_delayed_2	std_logic_vector ( 10 downto 0 )
waddr_reg_delayed_1	std_logic_vector ( 10 downto 0 )
waddr_reg_delayed_3	std_logic_vector ( 10 downto 0 )
datain_reg_delayed_1	std_logic
datain_reg_delayed_2	std_logic
datain_reg_delayed_3	std_logic
clk0_delayed	std_logic
Component Instantiations
datainsel	mux21 <Entity mux21>
datainregclr	nmux21 <Entity nmux21>
waddrsel	bmux21 <Entity bmux21>
waddrregclr	nmux21 <Entity nmux21>
weregclr	nmux21 <Entity nmux21>
wesel2	mux21 <Entity mux21>
wesel1	mux21 <Entity mux21>
raddrsel	bmux21 <Entity bmux21>
raddrregclr	nmux21 <Entity nmux21>
resel	mux21 <Entity mux21>
dataoutsel	mux21 <Entity mux21>
dataoutregclr	nmux21 <Entity nmux21>
raddrclksel	mux21 <Entity mux21>
raddrensel	mux21 <Entity mux21>
reclksel	mux21 <Entity mux21>
reensel	mux21 <Entity mux21>
reregclr	nmux21 <Entity nmux21>
dataoutensel	mux21 <Entity mux21>
dinreg	dffe <Entity dffe>
wereg	dffe <Entity dffe>
wedelaybuf	and1 <Entity and1>
clk0weregdelaybuf	and1 <Entity and1>
rereg	dffe <Entity dffe>
dataoutreg	dffe <Entity dffe>
waddrreg_0	dffe <Entity dffe>
waddrreg_1	dffe <Entity dffe>
waddrreg_2	dffe <Entity dffe>
waddrreg_3	dffe <Entity dffe>
waddrreg_4	dffe <Entity dffe>
waddrreg_5	dffe <Entity dffe>
waddrreg_6	dffe <Entity dffe>
waddrreg_7	dffe <Entity dffe>
waddrreg_8	dffe <Entity dffe>
waddrreg_9	dffe <Entity dffe>
waddrreg_10	dffe <Entity dffe>
raddrreg_0	dffe <Entity dffe>
raddrreg_1	dffe <Entity dffe>
raddrreg_2	dffe <Entity dffe>
raddrreg_3	dffe <Entity dffe>
raddrreg_4	dffe <Entity dffe>
raddrreg_5	dffe <Entity dffe>
raddrreg_6	dffe <Entity dffe>
raddrreg_7	dffe <Entity dffe>
raddrreg_8	dffe <Entity dffe>
raddrreg_9	dffe <Entity dffe>
raddrreg_10	dffe <Entity dffe>
flexmem	flex10ke_asynch_mem <Entity flex10ke_asynch_mem>

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Member Data Documentation

and1 [Component]

Reimplemented in flex10ke_ram_slice.

bmux21 [Component]

Reimplemented in flex10ke_ram_slice.

clk0_delayed std_logic [Signal]

clk0weregdelaybuf and1 [Component Instantiation]

datain_clr std_logic [Signal]

datain_int std_logic [Signal]

datain_reg std_logic [Signal]

datain_reg_clr std_logic [Signal]

datain_reg_clr_sel std_logic [Signal]

datain_reg_delayed_1 std_logic [Signal]

datain_reg_delayed_2 std_logic [Signal]

datain_reg_delayed_3 std_logic [Signal]

datain_reg_sel std_logic [Signal]

datainregclr nmux21 [Component Instantiation]

datainsel mux21 [Component Instantiation]

dataout_en_sel std_logic [Signal]

dataout_int std_logic [Signal]

dataout_reg std_logic [Signal]

dataout_reg_clr std_logic [Signal]

dataout_reg_clr_sel std_logic [Signal]

dataout_reg_sel std_logic [Signal]

dataout_tmp std_logic [Signal]

dataouten std_logic [Signal]

dataoutensel mux21 [Component Instantiation]

dataoutreg dffe [Component Instantiation]

dataoutreg_clr std_logic [Signal]

dataoutregclr nmux21 [Component Instantiation]

dataoutsel mux21 [Component Instantiation]

dffe [Component]

Reimplemented in flex10ke_ram_slice.

dinreg dffe [Component Instantiation]

dinreg_clr std_logic [Signal]

flex10ke_asynch_mem [Component]

Reimplemented in flex10ke_ram_slice.

flexmem flex10ke_asynch_mem [Component Instantiation]

mux21 [Component]

Reimplemented in flex10ke_ram_slice.

NC std_logic := ' 0 ' [Signal]

nmux21 [Component]

Reimplemented in flex10ke_ram_slice.

raddr_clk std_logic [Signal]

raddr_clk_sel std_logic [Signal]

raddr_en_sel std_logic [Signal]

raddr_int std_logic_vector ( 10 downto 0 ) [Signal]

raddr_num integer [Signal]

raddr_reg std_logic_vector ( 10 downto 0 ) [Signal]

raddr_reg_clr std_logic [Signal]

raddr_reg_clr_sel std_logic [Signal]

raddr_reg_sel std_logic [Signal]

raddrclksel mux21 [Component Instantiation]

raddren std_logic [Signal]

raddrensel mux21 [Component Instantiation]

raddrreg_0 dffe [Component Instantiation]

raddrreg_1 dffe [Component Instantiation]

raddrreg_10 dffe [Component Instantiation]

raddrreg_2 dffe [Component Instantiation]

raddrreg_3 dffe [Component Instantiation]

raddrreg_4 dffe [Component Instantiation]

raddrreg_5 dffe [Component Instantiation]

raddrreg_6 dffe [Component Instantiation]

raddrreg_7 dffe [Component Instantiation]

raddrreg_8 dffe [Component Instantiation]

raddrreg_9 dffe [Component Instantiation]

raddrreg_clr std_logic [Signal]

raddrregclr nmux21 [Component Instantiation]

raddrsel bmux21 [Component Instantiation]

re_clk std_logic [Signal]

re_clk_sel std_logic [Signal]

re_en_sel std_logic [Signal]

re_int std_logic [Signal]

re_reg std_logic [Signal]

re_reg_clr std_logic [Signal]

re_reg_clr_sel std_logic [Signal]

re_reg_sel std_logic [Signal]

reclksel mux21 [Component Instantiation]

reen std_logic [Signal]

reensel mux21 [Component Instantiation]

rereg dffe [Component Instantiation]

rereg_clr std_logic [Signal]

reregclr nmux21 [Component Instantiation]

resel mux21 [Component Instantiation]

valid_addr std_logic [Signal]

waddr_int std_logic_vector ( 10 downto 0 ) [Signal]

waddr_reg std_logic_vector ( 10 downto 0 ) [Signal]

waddr_reg_clr std_logic [Signal]

waddr_reg_clr_sel std_logic [Signal]

waddr_reg_delayed_1 std_logic_vector ( 10 downto 0 ) [Signal]

waddr_reg_delayed_2 std_logic_vector ( 10 downto 0 ) [Signal]

waddr_reg_delayed_3 std_logic_vector ( 10 downto 0 ) [Signal]

waddrreg_0 dffe [Component Instantiation]

waddrreg_1 dffe [Component Instantiation]

waddrreg_10 dffe [Component Instantiation]

waddrreg_2 dffe [Component Instantiation]

waddrreg_3 dffe [Component Instantiation]

waddrreg_4 dffe [Component Instantiation]

waddrreg_5 dffe [Component Instantiation]

waddrreg_6 dffe [Component Instantiation]

waddrreg_7 dffe [Component Instantiation]

waddrreg_8 dffe [Component Instantiation]

waddrreg_9 dffe [Component Instantiation]

waddrreg_clr std_logic [Signal]

waddrregclr nmux21 [Component Instantiation]

waddrsel bmux21 [Component Instantiation]

we_int std_logic [Signal]

we_pulse std_logic [Signal]

we_reg std_logic [Signal]

we_reg_clr std_logic [Signal]

we_reg_clr_sel std_logic [Signal]

we_reg_mux std_logic [Signal]

we_reg_mux_delayed std_logic [Signal]

wedelaybuf and1 [Component Instantiation]

wereg dffe [Component Instantiation]

wereg_clr std_logic [Signal]

weregclr nmux21 [Component Instantiation]

wesel1 mux21 [Component Instantiation]

wesel2 mux21 [Component Instantiation]

write_reg_sel std_logic [Signal]

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The documentation for this class was generated from the following file:

• flex10ke/flex10ke_atoms.vhd