Architectures | |
arch | Architecture |
Libraries | |
IEEE | |
Packages | |
std_logic_1164 | |
VITAL_Timing | |
VITAL_Primitives | |
atom_pack | Package <atom_pack> |
Generics | |
operation_mode | string := " input " |
reg_source_mode | string := " none " |
feedback_mode | string := " from_pin " |
power_up | string := " low " |
open_drain_output | string := " false " |
Ports | |
clk | in std_logic := ' 0 ' |
datain | in std_logic := ' 1 ' |
aclr | in std_logic := ' 0 ' |
ena | in std_logic := ' 1 ' |
oe | in std_logic := ' 1 ' |
devclrn | in std_logic := ' 1 ' |
devpor | in std_logic := ' 1 ' |
devoe | in std_logic := ' 0 ' |
padio | inout std_logic |
dataout | out std_logic |
aclr in std_logic := ' 0 ' [Port] |
atom_pack package [Package] |
clk in std_logic := ' 0 ' [Port] |
datain in std_logic := ' 1 ' [Port] |
dataout out std_logic [Port] |
devclrn in std_logic := ' 1 ' [Port] |
devoe in std_logic := ' 0 ' [Port] |
devpor in std_logic := ' 1 ' [Port] |
ena in std_logic := ' 1 ' [Port] |
feedback_mode string := " from_pin " [Generic] |
flex10ke_asynch_io package [Package] |
Reimplemented from arch.
IEEE library [Library] |
oe in std_logic := ' 1 ' [Port] |
open_drain_output string := " false " [Generic] |
operation_mode string := " input " [Generic] |
padio inout std_logic [Port] |
power_up string := " low " [Generic] |
reg_source_mode string := " none " [Generic] |
std_logic_1164 package [Package] |
VITAL_Primitives package [Package] |
VITAL_Timing package [Package] |