rtl Architecture Reference
[Model of ALTRO chip]

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
p_busFFF	( clk2 , rstb )
Signals
eq_i	std_logic
	Equal.
w1_i	std_logic
	Wire 1.
w0_i	std_logic
	Wire 0.
w2_i	std_logic_vector ( 7 downto 0 )
	wire 2
hadd_r_i	std_logic_vector ( 7 downto 0 )
	hardware address
Component Instantiations
i_glitch	glitchf <Entity glitchf>
	Trigger glitch filter.
i_sync1	sync221 <Entity sync221>
	Sync l2 to both clocks.

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Detailed Description

Architecture of bus interface

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Member Function Documentation

[Process]

p_busFFF		( clk2 ,
		rstb )

Decode address

Parameters:

	clk2	Clock
	rstb	Async reset

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Member Data Documentation

eq_i std_logic [Signal]

Equal.

hadd_r_i std_logic_vector ( 7 downto 0 ) [Signal]

hardware address

i_glitch glitchf [Component Instantiation]

Trigger glitch filter.

i_sync1 sync221 [Component Instantiation]

Sync l2 to both clocks.

w0_i std_logic [Signal]

Wire 0.

w1_i std_logic [Signal]

Wire 1.

w2_i std_logic_vector ( 7 downto 0 ) [Signal]

wire 2

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The documentation for this class was generated from the following file:

• altro/busint.vhd