trigger_box Entity Reference

Inheritance diagram for trigger_box:

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Collaboration diagram for trigger_box:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
glitch_filter_pack	Package <glitch_filter_pack>
Generics
GLITCH	boolean := false
L0_DUR	integer range 1 to 16 := 1
L1_DUR	integer range 1 to 16 := 8
L2_DUR	integer range 1 to 16 := 8
Ports
clk	in std_logic
rstb	in std_logic
start	in std_logic
l0_only	in std_logic
inhibit	in std_logic
l0	in std_logic
l1b	in std_logic
l2b	in std_logic
l1_timeout	in std_logic_vector ( 15 downto 0 )
l2_timeout	in std_logic_vector ( 15 downto 0 )
l0_out	out std_logic
l1b_out	out std_logic
l2b_out	out std_logic
l1r	out std_logic
l2r	out std_logic
busy	out std_logic
timeout	out std_logic
overlap	out std_logic

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Member Data Documentation

busy out std_logic [Port]

clk in std_logic [Port]

GLITCH boolean := false [Generic]

glitch_filter_pack package [Package]

ieee library [Library]

inhibit in std_logic [Port]

l0 in std_logic [Port]

L0_DUR integer range 1 to 16 := 1 [Generic]

l0_only in std_logic [Port]

l0_out out std_logic [Port]

L1_DUR integer range 1 to 16 := 8 [Generic]

l1_timeout in std_logic_vector ( 15 downto 0 ) [Port]

l1b in std_logic [Port]

l1b_out out std_logic [Port]

l1r out std_logic [Port]

L2_DUR integer range 1 to 16 := 8 [Generic]

l2_timeout in std_logic_vector ( 15 downto 0 ) [Port]

l2b in std_logic [Port]

l2b_out out std_logic [Port]

l2r out std_logic [Port]

numeric_std package [Package]

overlap out std_logic [Port]

rstb in std_logic [Port]

start in std_logic [Port]

std_logic_1164 package [Package]

timeout out std_logic [Port]

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The documentation for this class was generated from the following file:

• bc/fmdd/trigger_box/trigger_box.vhd