rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
glitch_meta_filter	( clk , rstb )
Signals
dout_mux_i	std_logic_vector ( 39 downto 0 )
dout_i	std_logic_vector ( 39 downto 0 )
en_addr_i	std_logic
en_data_i	std_logic
error_fedge_i	std_logic
error_i	std_logic
error_ii	std_logic
error_iii	std_logic
Component Instantiations
mux	mux_bus <Entity mux_bus>

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Member Function Documentation

[Process]

glitch_meta_filter		( clk ,
		rstb )

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Member Data Documentation

dout_i std_logic_vector ( 39 downto 0 ) [Signal]

dout_mux_i std_logic_vector ( 39 downto 0 ) [Signal]

en_addr_i std_logic [Signal]

en_data_i std_logic [Signal]

error_fedge_i std_logic [Signal]

error_i std_logic [Signal]

error_ii std_logic [Signal]

error_iii std_logic [Signal]

mux mux_bus [Component Instantiation]

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The documentation for this class was generated from the following file:

• bc/drivers/signals_driver/signals_driver.vhd