rtl2 Architecture Reference
Inheritance diagram for rtl2:
Collaboration diagram for rtl2:
Processes | |
| enable_edge | ( clk , rstb ) |
| counter | ( clk_i , rstb , clear ) |
| shift_reg | ( clk_i , rstb ) |
Signals | |
| cnt_i | unsigned ( 3 downto 0 ) |
| reg_i | std_logic_vector ( 7 downto 0 ) |
| clk_i | std_logic |
Member Function Documentation
| counter | ( clk_i , | |
| rstb , | ||
| clear ) |
| enable_edge | ( clk , | |
| rstb ) |
| shift_reg | ( clk_i , | |
| rstb ) |
Member Data Documentation
clk_i std_logic [Signal] |
cnt_i unsigned ( 3 downto 0 ) [Signal] |
reg_i std_logic_vector ( 7 downto 0 ) [Signal] |
The documentation for this class was generated from the following file:
- bc/bc_core/slave/serializer_bc/serializer_bc.vhd
