clear | serializer_bc | [Port] |
clk | serializer_bc | [Port] |
clk_i | rtl2 | [Signal] |
cnt_8 | serializer_bc | [Port] |
serializer_bc::rtl.cnt_i | rtl | [Signal] |
serializer_bc::rtl2.cnt_i | rtl2 | [Signal] |
serializer_bc::rtl.counter(clk, rstb) | rtl | [Process] |
serializer_bc::rtl2.counter(clk_i, rstb, clear) | rtl2 | [Process] |
data | serializer_bc | [Port] |
enable | serializer_bc | [Port] |
serializer_bc::rtl.enable_edge(clk, rstb) | rtl | [Process] |
serializer_bc::rtl2.enable_edge(clk, rstb) | rtl2 | [Process] |
ieee | serializer_bc | [Library] |
load | serializer_bc | [Port] |
numeric_std | serializer_bc | [Package] |
old_en_i | rtl | [Signal] |
q | serializer_bc | [Port] |
serializer_bc::rtl.reg_i | rtl | [Signal] |
serializer_bc::rtl2.reg_i | rtl2 | [Signal] |
rstb | serializer_bc | [Port] |
serializer_bc::rtl.shift_reg(clk, rstb) | rtl | [Process] |
serializer_bc::rtl2.shift_reg(clk_i, rstb) | rtl2 | [Process] |
shiftin | serializer_bc | [Port] |
shiftout | serializer_bc | [Port] |
std_logic_1164 | serializer_bc | [Package] |