rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
next_state	( clk , rstb )
fsm	( st_i , exec , ready , data_valid , error , start_i , stop_i )
counter_for_ib	( clk , rstb )
result_output	( clk , rstb )
Constants
seq_start	std_logic_vector ( 1 downto 0 ) := " 10 "
seq_stop	std_logic_vector ( 1 downto 0 ) := " 00 "
seq_write	std_logic_vector ( 1 downto 0 ) := " 11 "
seq_read	std_logic_vector ( 1 downto 0 ) := " 01 "
Types
st_t	( idle , read_im , load_data , wait_ready , inc_cnt_ib , wait_instr , end_instr )
Signals
st_i	st_t
nx_st_i	st_t
start_i	std_logic
stop_i	std_logic
cnt_en_ib_i	std_logic
reset_add_i	std_logic
seq_active_i	std_logic
add_ib_i	unsigned ( 2 downto 0 )

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Member Function Documentation

[Process]

counter_for_ib		( clk ,
		rstb )

[Process]

fsm		( st_i ,
		exec ,
		ready ,
		data_valid ,
		error ,
		start_i ,
		stop_i )

[Process]

next_state		( clk ,
		rstb )

[Process]

result_output		( clk ,
		rstb )

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Member Data Documentation

add_ib_i unsigned ( 2 downto 0 ) [Signal]

cnt_en_ib_i std_logic [Signal]

nx_st_i st_t [Signal]

reset_add_i std_logic [Signal]

seq_active_i std_logic [Signal]

seq_read std_logic_vector ( 1 downto 0 ) := " 01 " [Constant]

seq_start std_logic_vector ( 1 downto 0 ) := " 10 " [Constant]

seq_stop std_logic_vector ( 1 downto 0 ) := " 00 " [Constant]

seq_write std_logic_vector ( 1 downto 0 ) := " 11 " [Constant]

st_i st_t [Signal]

st_t ( idle , read_im , load_data , wait_ready , inc_cnt_ib , wait_instr , end_instr ) [Type]

start_i std_logic [Signal]

stop_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• msmodule/msm_lsc_core/msm_sequencer_rcu/msm_sequencer_rcu.vhd