

Architectures | |
| STRUCTURE | Architecture |
Libraries | |
| IEEE | |
| UNISIM | |
Packages | |
| STD_LOGIC_1164 | |
| VCOMPONENTS | |
| VPKG | |
Ports | |
| en | in std_logic := ' x ' |
| clk | in std_logic := ' x ' |
| we | in std_logic := ' x ' |
| dout | out std_logic_vector ( 15 downto 0 ) |
| din | in std_logic_vector ( 15 downto 0 ) |
| addr | in std_logic_vector ( 3 downto 0 ) |
addr in std_logic_vector ( 3 downto 0 ) [Port] |
clk in std_logic := ' x ' [Port] |
din in std_logic_vector ( 15 downto 0 ) [Port] |
dout out std_logic_vector ( 15 downto 0 ) [Port] |
en in std_logic := ' x ' [Port] |
IEEE library [Library] |
STD_LOGIC_1164 package [Package] |
UNISIM library [Library] |
VCOMPONENTS package [Package] |
VPKG package [Package] |
we in std_logic := ' x ' [Port] |
1.6.2-20100208