msm2_st_mem Entity Reference

Inheritance diagram for msm2_st_mem:
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Collaboration diagram for msm2_st_mem:
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List of all members.



Architectures

STRUCTURE Architecture

Libraries

IEEE 
UNISIM 

Packages

STD_LOGIC_1164 
VCOMPONENTS 
VPKG 

Ports

en  in std_logic := ' x '
clk  in std_logic := ' x '
we  in std_logic := ' x '
dout  out std_logic_vector ( 15 downto 0 )
din  in std_logic_vector ( 15 downto 0 )
addr  in std_logic_vector ( 3 downto 0 )

Member Data Documentation

addr in std_logic_vector ( 3 downto 0 ) [Port]
clk in std_logic := ' x ' [Port]
din in std_logic_vector ( 15 downto 0 ) [Port]
dout out std_logic_vector ( 15 downto 0 ) [Port]
en in std_logic := ' x ' [Port]
IEEE library [Library]
STD_LOGIC_1164 package [Package]
UNISIM library [Library]
VCOMPONENTS package [Package]
VPKG package [Package]
we in std_logic := ' x ' [Port]

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