addr | msm2_st_mem | [Port] |
addr_2 | STRUCTURE | [Signal] |
B6 | STRUCTURE | [Component Instantiation] |
clk | msm2_st_mem | [Port] |
din | msm2_st_mem | [Port] |
din_3 | STRUCTURE | [Signal] |
dout | msm2_st_mem | [Port] |
dout_4 | STRUCTURE | [Signal] |
en | msm2_st_mem | [Port] |
GND_1 | STRUCTURE | [Component Instantiation] |
IEEE | msm2_st_mem | [Library] |
N0 | STRUCTURE | [Signal] |
NLW_B6_DOP_0_UNCONNECTED | STRUCTURE | [Signal] |
NLW_B6_DOP_1_UNCONNECTED | STRUCTURE | [Signal] |
NLW_VCC_P_UNCONNECTED | STRUCTURE | [Signal] |
STD_LOGIC_1164 | msm2_st_mem | [Package] |
UNISIM | msm2_st_mem | [Library] |
VCC_0 | STRUCTURE | [Component Instantiation] |
VCOMPONENTS | msm2_st_mem | [Package] |
VPKG | msm2_st_mem | [Package] |
we | msm2_st_mem | [Port] |