arch_err_hndlr Architecture Reference

Inheritance diagram for arch_err_hndlr:

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Collaboration diagram for arch_err_hndlr:

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List of all members.

Functions
integer	conv_integer ( constant input: in std_logic_vector )
Processes
PROCESS_26	( set_act , clk , hard_err , fec_add , safty_en , reslt_reg )
PROCESS_27	( clk , soft_err , hard_err , fec_add , safty_en , reslt_reg )
Signals
soft_err	std_logic := ' 0 '
hard_err	std_logic := ' 0 '
fect_act	std_logic := ' 0 '
reg_rdo_list	std_logic_vector ( 15 downto 0 ) := X " FFFF "
reg_act_list	std_logic_vector ( 15 downto 0 ) := X " FFFF "
sft_err0	std_logic := ' 0 '
sft_err1	std_logic := ' 0 '
sft_err2	std_logic := ' 0 '
sft_err3	std_logic := ' 0 '
sft_err4	std_logic := ' 0 '
sft_err5	std_logic := ' 0 '
sft_err6	std_logic := ' 0 '
sft_err7	std_logic := ' 0 '
hrd_err0	std_logic := ' 0 '
hrd_err1	std_logic := ' 0 '
hrd_err2	std_logic := ' 0 '
hrd_err3	std_logic := ' 0 '
hrd_err4	std_logic := ' 0 '
hrd_err5	std_logic := ' 0 '
hrd_err6	std_logic := ' 0 '
hrd_err7	std_logic := ' 0 '
tmp_ov_th	std_logic := ' 0 '
av_un_th	std_logic := ' 0 '
ac_ov_th	std_logic := ' 0 '
dv_un_th	std_logic := ' 0 '
dc_ov_th	std_logic := ' 0 '
paps_err	std_logic := ' 0 '
alps_err	std_logic := ' 0 '
misd_sclk	std_logic := ' 0 '

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Member Function Documentation

[Function]

integer conv_integer

(constant input in std_logic_vector )

[Process]

PROCESS_26		( set_act ,
		clk ,
		hard_err ,
		fec_add ,
		safty_en ,
		reslt_reg )

[Process]

PROCESS_27		( clk ,
		soft_err ,
		hard_err ,
		fec_add ,
		safty_en ,
		reslt_reg )

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Member Data Documentation

ac_ov_th std_logic := ' 0 ' [Signal]

alps_err std_logic := ' 0 ' [Signal]

av_un_th std_logic := ' 0 ' [Signal]

dc_ov_th std_logic := ' 0 ' [Signal]

dv_un_th std_logic := ' 0 ' [Signal]

fect_act std_logic := ' 0 ' [Signal]

hard_err std_logic := ' 0 ' [Signal]

hrd_err0 std_logic := ' 0 ' [Signal]

hrd_err1 std_logic := ' 0 ' [Signal]

hrd_err2 std_logic := ' 0 ' [Signal]

hrd_err3 std_logic := ' 0 ' [Signal]

hrd_err4 std_logic := ' 0 ' [Signal]

hrd_err5 std_logic := ' 0 ' [Signal]

hrd_err6 std_logic := ' 0 ' [Signal]

hrd_err7 std_logic := ' 0 ' [Signal]

misd_sclk std_logic := ' 0 ' [Signal]

paps_err std_logic := ' 0 ' [Signal]

reg_act_list std_logic_vector ( 15 downto 0 ) := X " FFFF " [Signal]

reg_rdo_list std_logic_vector ( 15 downto 0 ) := X " FFFF " [Signal]

sft_err0 std_logic := ' 0 ' [Signal]

sft_err1 std_logic := ' 0 ' [Signal]

sft_err2 std_logic := ' 0 ' [Signal]

sft_err3 std_logic := ' 0 ' [Signal]

sft_err4 std_logic := ' 0 ' [Signal]

sft_err5 std_logic := ' 0 ' [Signal]

sft_err6 std_logic := ' 0 ' [Signal]

sft_err7 std_logic := ' 0 ' [Signal]

soft_err std_logic := ' 0 ' [Signal]

tmp_ov_th std_logic := ' 0 ' [Signal]

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The documentation for this class was generated from the following file:

• msmodule2/msm2_inthandler/msm2_err_hndl/msm2_err_hndl.vhd