rtl Architecture Reference
[Model of ALTRO chip]

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
p_sync	( clk2 , rstb )
p_fsm	( st_i , cstb , cs , done , chrdo , valid , rdo_done )
Constants
s_idle	std_logic_vector ( 5 downto 0 ) := " 000000 "
s_decode1	std_logic_vector ( 5 downto 0 ) := " 000111 "
s_decode2	std_logic_vector ( 5 downto 0 ) := " 011001 "
s_exec	std_logic_vector ( 5 downto 0 ) := " 011110 "
s_en1	std_logic_vector ( 5 downto 0 ) := " 101010 "
s_ack	std_logic_vector ( 5 downto 0 ) := " 101101 "
s_en2	std_logic_vector ( 5 downto 0 ) := " 110011 "
s_rdo	std_logic_vector ( 5 downto 0 ) := " 110100 "
Signals
next_st_i	std_logic_vector ( 5 downto 0 )
st_i	std_logic_vector ( 5 downto 0 )

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Detailed Description

Decode exection of bus instructions

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Member Function Documentation

[Process]

p_fsm		( st_i ,
		cstb ,
		cs ,
		done ,
		chrdo ,
		valid ,
		rdo_done )

Hamming protected state machine.

Parameters:

	st_i	State
	cstb	Control strobe
	cs	Card/channel selected
	done	Done decoding (?)
	chrdo	Channel read-out
	valid	Valid instruction
	rdo_done	Read-out done

[Process]

p_sync		( clk2 ,
		rstb )

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Member Data Documentation

next_st_i std_logic_vector ( 5 downto 0 ) [Signal]

s_ack std_logic_vector ( 5 downto 0 ) := " 101101 " [Constant]

s_decode1 std_logic_vector ( 5 downto 0 ) := " 000111 " [Constant]

s_decode2 std_logic_vector ( 5 downto 0 ) := " 011001 " [Constant]

s_en1 std_logic_vector ( 5 downto 0 ) := " 101010 " [Constant]

s_en2 std_logic_vector ( 5 downto 0 ) := " 110011 " [Constant]

s_exec std_logic_vector ( 5 downto 0 ) := " 011110 " [Constant]

s_idle std_logic_vector ( 5 downto 0 ) := " 000000 " [Constant]

s_rdo std_logic_vector ( 5 downto 0 ) := " 110100 " [Constant]

st_i std_logic_vector ( 5 downto 0 ) [Signal]

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The documentation for this class was generated from the following file:

• altro/intrech.vhd