ack | intrech | [Port] |
chrdo | intrech | [Port] |
clk2 | intrech | [Port] |
cs | intrech | [Port] |
cstb | intrech | [Port] |
decode | intrech | [Port] |
done | intrech | [Port] |
en1 | intrech | [Port] |
en2 | intrech | [Port] |
exec | intrech | [Port] |
exrdo | intrech | [Port] |
h_abt | intrech | [Port] |
h_err | intrech | [Port] |
idle | intrech | [Port] |
ieee | intrech | [Library] |
next_st_i | rtl | [Signal] |
p_fsm(st_i, cstb, cs, done, chrdo, valid, rdo_done) | rtl | [Process] |
p_sync(clk2, rstb) | rtl | [Process] |
rdo_done | intrech | [Port] |
rstb | intrech | [Port] |
s_ack | rtl | [Constant] |
s_decode1 | rtl | [Constant] |
s_decode2 | rtl | [Constant] |
s_en1 | rtl | [Constant] |
s_en2 | rtl | [Constant] |
s_exec | rtl | [Constant] |
s_idle | rtl | [Constant] |
s_rdo | rtl | [Constant] |
st_i | rtl | [Signal] |
std_logic_1164 | intrech | [Package] |
valid | intrech | [Port] |