rtl Architecture Reference
[Model of ALTRO chip]

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
p_sync	( clk2 , rstb )
p_fsm	( st_i , exrdo , ch_red )
Constants
s_idle	std_logic_vector ( 4 downto 0 ) := " 00000 "
s_rdo	std_logic_vector ( 4 downto 0 ) := " 00111 "
s_wait	std_logic_vector ( 4 downto 0 ) := " 11001 "
s_done	std_logic_vector ( 4 downto 0 ) := " 11110 "
Signals
next_st_i	std_logic_vector ( 4 downto 0 )
st_i	std_logic_vector ( 4 downto 0 )

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Detailed Description

Read-out module

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Member Function Documentation

[Process]

p_fsm		( st_i ,
		exrdo ,
		ch_red )

Hamming protected state machine

Parameters:

	st_i	State
	exrdo	Execute read-out
	ch_red	Channel read-out

[Process]

p_sync		( clk2 ,
		rstb )

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Member Data Documentation

next_st_i std_logic_vector ( 4 downto 0 ) [Signal]

s_done std_logic_vector ( 4 downto 0 ) := " 11110 " [Constant]

s_idle std_logic_vector ( 4 downto 0 ) := " 00000 " [Constant]

s_rdo std_logic_vector ( 4 downto 0 ) := " 00111 " [Constant]

s_wait std_logic_vector ( 4 downto 0 ) := " 11001 " [Constant]

st_i std_logic_vector ( 4 downto 0 ) [Signal]

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The documentation for this class was generated from the following file:

• altro/intrdoh.vhd