| ack | intctrl | [Port] |
| altro_model | intctrl | [Library] |
| ch_red | intctrl | [Port] |
| chrdo | intctrl | [Port] |
| clk2 | intctrl | [Port] |
| cs | intctrl | [Port] |
| cstb | intctrl | [Port] |
| decode_i | rtl | [Signal] |
| done | intctrl | [Port] |
| en1 | intctrl | [Port] |
| en2 | intctrl | [Port] |
| exec | intctrl | [Port] |
| exec_i | rtl | [Signal] |
| exrdo_i | rtl | [Signal] |
| h_abt | intctrl | [Port] |
| h_abt0_i | rtl | [Signal] |
| h_abt1_i | rtl | [Signal] |
| h_err | intctrl | [Port] |
| h_err0_i | rtl | [Signal] |
| h_err1_i | rtl | [Signal] |
| i_rdo | rtl | [Component Instantiation] |
| i_rec | rtl | [Component Instantiation] |
| idle_i | rtl | [Signal] |
| ieee | intctrl | [Library] |
| intrdoh_pack | intctrl | [Package] |
| intrech_pack | intctrl | [Package] |
| load | intctrl | [Port] |
| loadcs | intctrl | [Port] |
| rdo | intctrl | [Port] |
| rdo_done_i | rtl | [Signal] |
| rstb | intctrl | [Port] |
| std_logic_1164 | intctrl | [Package] |
| valid | intctrl | [Port] |
| waitst | intctrl | [Port] |
1.6.2-20100208