rtl Architecture Reference
[Model of ALTRO chip]

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
p_filter	( clk , rstb )
Signals
w0_i	std_logic
r1_i	std_logic
r2_i	std_logic
r3_i	std_logic
x1_i	std_logic

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Detailed Description

A glitch filter

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Member Function Documentation

[Process]

p_filter		( clk ,
		rstb )

The filter

Parameters:

	clk	Clock
	rstb	Async. reset

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Member Data Documentation

r1_i std_logic [Signal]

r2_i std_logic [Signal]

r3_i std_logic [Signal]

w0_i std_logic [Signal]

x1_i std_logic [Signal]

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The documentation for this class was generated from the following file:

• altro/glitchf.vhd