fmdd Entity Reference

Inheritance diagram for fmdd:

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Collaboration diagram for fmdd:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
work
Packages
std_logic_1164
interpreter_pack	Package <interpreter_pack>
trigger_handler_pack	Package <trigger_handler_pack>
trigger_box_pack	Package <trigger_box_pack>
dac_interface_pack	Package <dac_interface_pack>
va1_readout_pack	Package <va1_readout_pack>
clock_gen_pack	Package <clock_gen_pack>
cal_manager_pack	Package <cal_manager_pack>
Ports
clk	in std_logic
	Clock.
sclk	in std_logic
	Sample clock.
rstb	in std_logic
	Async reset.
l0	in std_logic
	L0 trigger.
l1b	in std_logic
	L1 trigger.
l2b	in std_logic
	L2 trigger.
hold_wait	in std_logic_vector ( 15 downto 0 )
	Wait to hold.
l1_timeout	in std_logic_vector ( 15 downto 0 )
	L1 timeout.
l2_timeout	in std_logic_vector ( 15 downto 0 )
	L2 timeout.
busy	out std_logic
	Busy signal.
l2r	out std_logic
	L2 reject (timeout).
shift_div	in std_logic_vector ( 15 downto 0 )
	Shift clock params.
shift_in	out std_logic
	Shift reg. reset to VA1s (-).
shift_clk	out std_logic
	Shift clock to VA1s (-).
strips	in std_logic_vector ( 15 downto 0 )
	Strip range.
digital_reset	out std_logic
	Reset VA1s (+).
hold	out std_logic
	Hold values in VA1 (-).
cal_level	in std_logic_vector ( 15 downto 0 )
	Cal. level.
cal_iter	in std_logic_vector ( 15 downto 0 )
	Cal. events.
cal_on	out std_logic
	Calib mode on (-).
cal_enable	out std_logic
	Enable cal step (-).
cal_delay	in std_logic_vector ( 15 downto 0 )
	Extra delay.
shape_bias	in std_logic_vector ( 15 downto 0 )
	Shape bias.
vfs	in std_logic_vector ( 15 downto 0 )
	Shape ref.
vfp	in std_logic_vector ( 15 downto 0 )
	Pre-amp. ref.
dac_addr	out std_logic_vector ( 11 downto 0 )
	DAC address.
dac_data	out std_logic_vector ( 7 downto 0 )
	DAC value.
sample_div	in std_logic_vector ( 15 downto 0 )
	Sample clock param.
sample_clk	out std_logic
	Sample clock to ALTROs.
altro_l1	out std_logic
	L1 to ALTROs.
altro_l2	out std_logic
	L2 to ALTROs.
command	in std_logic_vector ( 15 downto 0 )
	Commands.
status	out std_logic_vector ( 15 downto 0 )
debug	out std_logic_vector ( 14 downto 0 )
	Status.

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Member Data Documentation

altro_l1 out std_logic [Port]

L1 to ALTROs.

altro_l2 out std_logic [Port]

L2 to ALTROs.

busy out std_logic [Port]

Busy signal.

cal_delay in std_logic_vector ( 15 downto 0 ) [Port]

Extra delay.

cal_enable out std_logic [Port]

Enable cal step (-).

cal_iter in std_logic_vector ( 15 downto 0 ) [Port]

Cal. events.

cal_level in std_logic_vector ( 15 downto 0 ) [Port]

Cal. level.

cal_manager_pack package [Package]

cal_on out std_logic [Port]

Calib mode on (-).

clk in std_logic [Port]

Clock.

clock_gen_pack package [Package]

command in std_logic_vector ( 15 downto 0 ) [Port]

Commands.

dac_addr out std_logic_vector ( 11 downto 0 ) [Port]

DAC address.

dac_data out std_logic_vector ( 7 downto 0 ) [Port]

DAC value.

dac_interface_pack package [Package]

debug out std_logic_vector ( 14 downto 0 ) [Port]

Status.

digital_reset out std_logic [Port]

Reset VA1s (+).

hold out std_logic [Port]

Hold values in VA1 (-).

hold_wait in std_logic_vector ( 15 downto 0 ) [Port]

Wait to hold.

ieee library [Library]

interpreter_pack package [Package]

l0 in std_logic [Port]

L0 trigger.

l1_timeout in std_logic_vector ( 15 downto 0 ) [Port]

L1 timeout.

l1b in std_logic [Port]

L1 trigger.

l2_timeout in std_logic_vector ( 15 downto 0 ) [Port]

L2 timeout.

l2b in std_logic [Port]

L2 trigger.

l2r out std_logic [Port]

L2 reject (timeout).

rstb in std_logic [Port]

Async reset.

sample_clk out std_logic [Port]

Sample clock to ALTROs.

sample_div in std_logic_vector ( 15 downto 0 ) [Port]

Sample clock param.

sclk in std_logic [Port]

Sample clock.

shape_bias in std_logic_vector ( 15 downto 0 ) [Port]

Shape bias.

shift_clk out std_logic [Port]

Shift clock to VA1s (-).

shift_div in std_logic_vector ( 15 downto 0 ) [Port]

Shift clock params.

shift_in out std_logic [Port]

Shift reg. reset to VA1s (-).

status out std_logic_vector ( 15 downto 0 ) [Port]

std_logic_1164 package [Package]

strips in std_logic_vector ( 15 downto 0 ) [Port]

Strip range.

trigger_box_pack package [Package]

trigger_handler_pack package [Package]

va1_readout_pack package [Package]

vfp in std_logic_vector ( 15 downto 0 ) [Port]

Pre-amp. ref.

vfs in std_logic_vector ( 15 downto 0 ) [Port]

Shape ref.

work library [Library]

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The documentation for this class was generated from the following file:

• bc/fmdd/fmdd.vhd