flex10ke_ram_slice Member List

This is the complete list of members for flex10ke_ram_slice, including all inherited members.

address_width	flex10ke_ram_slice	`[Generic]`
and1	flex10ke_ram_slice	`[Package]`
atom_pack	flex10ke_ram_slice	`[Package]`
bit_number	flex10ke_ram_slice	`[Generic]`
bmux21	flex10ke_ram_slice	`[Package]`
clk0	flex10ke_ram_slice	`[Port]`
clk0_delayed	structure	`[Signal]`
clk0weregdelaybuf	structure	`[Component Instantiation]`
clk1	flex10ke_ram_slice	`[Port]`
clr0	flex10ke_ram_slice	`[Port]`
data_in_clear	flex10ke_ram_slice	`[Generic]`
data_in_clock	flex10ke_ram_slice	`[Generic]`
data_out_clear	flex10ke_ram_slice	`[Generic]`
data_out_clock	flex10ke_ram_slice	`[Generic]`
datain	flex10ke_ram_slice	`[Port]`
datain_clr	structure	`[Signal]`
datain_int	structure	`[Signal]`
datain_reg	structure	`[Signal]`
datain_reg_clr	structure	`[Signal]`
datain_reg_clr_sel	structure	`[Signal]`
datain_reg_delayed_1	structure	`[Signal]`
datain_reg_delayed_2	structure	`[Signal]`
datain_reg_delayed_3	structure	`[Signal]`
datain_reg_sel	structure	`[Signal]`
datainregclr	structure	`[Component Instantiation]`
datainsel	structure	`[Component Instantiation]`
dataout	flex10ke_ram_slice	`[Port]`
dataout_en_sel	structure	`[Signal]`
dataout_int	structure	`[Signal]`
dataout_reg	structure	`[Signal]`
dataout_reg_clr	structure	`[Signal]`
dataout_reg_clr_sel	structure	`[Signal]`
dataout_reg_sel	structure	`[Signal]`
dataout_tmp	structure	`[Signal]`
dataouten	structure	`[Signal]`
dataoutensel	structure	`[Component Instantiation]`
dataoutreg	structure	`[Component Instantiation]`
dataoutreg_clr	structure	`[Signal]`
dataoutregclr	structure	`[Component Instantiation]`
dataoutsel	structure	`[Component Instantiation]`
devclrn	flex10ke_ram_slice	`[Port]`
devpor	flex10ke_ram_slice	`[Port]`
dffe	flex10ke_ram_slice	`[Package]`
dinreg	structure	`[Component Instantiation]`
dinreg_clr	structure	`[Signal]`
ena0	flex10ke_ram_slice	`[Port]`
ena1	flex10ke_ram_slice	`[Port]`
first_address	flex10ke_ram_slice	`[Generic]`
flex10ke_asynch_mem	flex10ke_ram_slice	`[Package]`
flexmem	structure	`[Component Instantiation]`
IEEE	flex10ke_ram_slice	`[Library]`
init_file	flex10ke_ram_slice	`[Generic]`
last_address	flex10ke_ram_slice	`[Generic]`
logical_ram_depth	flex10ke_ram_slice	`[Generic]`
logical_ram_name	flex10ke_ram_slice	`[Generic]`
logical_ram_width	flex10ke_ram_slice	`[Generic]`
mem1	flex10ke_ram_slice	`[Generic]`
mem2	flex10ke_ram_slice	`[Generic]`
mem3	flex10ke_ram_slice	`[Generic]`
mem4	flex10ke_ram_slice	`[Generic]`
modesel	flex10ke_ram_slice	`[Port]`
mux21	flex10ke_ram_slice	`[Package]`
NC	structure	`[Signal]`
nmux21	flex10ke_ram_slice	`[Package]`
operation_mode	flex10ke_ram_slice	`[Generic]`
raddr	flex10ke_ram_slice	`[Port]`
raddr_clk	structure	`[Signal]`
raddr_clk_sel	structure	`[Signal]`
raddr_en_sel	structure	`[Signal]`
raddr_int	structure	`[Signal]`
raddr_num	structure	`[Signal]`
raddr_reg	structure	`[Signal]`
raddr_reg_clr	structure	`[Signal]`
raddr_reg_clr_sel	structure	`[Signal]`
raddr_reg_sel	structure	`[Signal]`
raddrclksel	structure	`[Component Instantiation]`
raddren	structure	`[Signal]`
raddrensel	structure	`[Component Instantiation]`
raddrreg_0	structure	`[Component Instantiation]`
raddrreg_1	structure	`[Component Instantiation]`
raddrreg_10	structure	`[Component Instantiation]`
raddrreg_2	structure	`[Component Instantiation]`
raddrreg_3	structure	`[Component Instantiation]`
raddrreg_4	structure	`[Component Instantiation]`
raddrreg_5	structure	`[Component Instantiation]`
raddrreg_6	structure	`[Component Instantiation]`
raddrreg_7	structure	`[Component Instantiation]`
raddrreg_8	structure	`[Component Instantiation]`
raddrreg_9	structure	`[Component Instantiation]`
raddrreg_clr	structure	`[Signal]`
raddrregclr	structure	`[Component Instantiation]`
raddrsel	structure	`[Component Instantiation]`
re	flex10ke_ram_slice	`[Port]`
re_clk	structure	`[Signal]`
re_clk_sel	structure	`[Signal]`
re_en_sel	structure	`[Signal]`
re_int	structure	`[Signal]`
re_reg	structure	`[Signal]`
re_reg_clr	structure	`[Signal]`
re_reg_clr_sel	structure	`[Signal]`
re_reg_sel	structure	`[Signal]`
read_address_clear	flex10ke_ram_slice	`[Generic]`
read_address_clock	flex10ke_ram_slice	`[Generic]`
read_enable_clear	flex10ke_ram_slice	`[Generic]`
read_enable_clock	flex10ke_ram_slice	`[Generic]`
reclksel	structure	`[Component Instantiation]`
reen	structure	`[Signal]`
reensel	structure	`[Component Instantiation]`
rereg	structure	`[Component Instantiation]`
rereg_clr	structure	`[Signal]`
reregclr	structure	`[Component Instantiation]`
resel	structure	`[Component Instantiation]`
std_logic_1164	flex10ke_ram_slice	`[Package]`
std_logic_unsigned	flex10ke_ram_slice	`[Package]`
valid_addr	structure	`[Signal]`
VITAL_Timing	flex10ke_ram_slice	`[Package]`
waddr	flex10ke_ram_slice	`[Port]`
waddr_int	structure	`[Signal]`
waddr_reg	structure	`[Signal]`
waddr_reg_clr	structure	`[Signal]`
waddr_reg_clr_sel	structure	`[Signal]`
waddr_reg_delayed_1	structure	`[Signal]`
waddr_reg_delayed_2	structure	`[Signal]`
waddr_reg_delayed_3	structure	`[Signal]`
waddrreg_0	structure	`[Component Instantiation]`
waddrreg_1	structure	`[Component Instantiation]`
waddrreg_10	structure	`[Component Instantiation]`
waddrreg_2	structure	`[Component Instantiation]`
waddrreg_3	structure	`[Component Instantiation]`
waddrreg_4	structure	`[Component Instantiation]`
waddrreg_5	structure	`[Component Instantiation]`
waddrreg_6	structure	`[Component Instantiation]`
waddrreg_7	structure	`[Component Instantiation]`
waddrreg_8	structure	`[Component Instantiation]`
waddrreg_9	structure	`[Component Instantiation]`
waddrreg_clr	structure	`[Signal]`
waddrregclr	structure	`[Component Instantiation]`
waddrsel	structure	`[Component Instantiation]`
we	flex10ke_ram_slice	`[Port]`
we_int	structure	`[Signal]`
we_pulse	structure	`[Signal]`
we_reg	structure	`[Signal]`
we_reg_clr	structure	`[Signal]`
we_reg_clr_sel	structure	`[Signal]`
we_reg_mux	structure	`[Signal]`
we_reg_mux_delayed	structure	`[Signal]`
wedelaybuf	structure	`[Component Instantiation]`
wereg	structure	`[Component Instantiation]`
wereg_clr	structure	`[Signal]`
weregclr	structure	`[Component Instantiation]`
wesel1	structure	`[Component Instantiation]`
wesel2	structure	`[Component Instantiation]`
write_address_clear	flex10ke_ram_slice	`[Generic]`
write_enable_clear	flex10ke_ram_slice	`[Generic]`
write_logic_clock	flex10ke_ram_slice	`[Generic]`
write_reg_sel	structure	`[Signal]`