flex10ke_lcell_register Entity Reference

Inheritance diagram for flex10ke_lcell_register:

[legend]

Collaboration diagram for flex10ke_lcell_register:

[legend]

List of all members.

Architectures
vital_le_reg	Architecture
Libraries
IEEE
Packages
std_logic_1164
VITAL_Timing
VITAL_Primitives
atom_pack	Package <atom_pack>
Generics
operation_mode	string := " normal "
clock_enable_mode	string := " false "
packed_mode	string := " false "
x_on_violation	string := " on "
TimingChecksOn	boolean := true
MsgOn	boolean := DefGlitchMsgOn
XOn	boolean := DefGlitchXOn
MsgOnChecks	boolean := DefMsgOnChecks
XOnChecks	boolean := DefXOnChecks
InstancePath	string := " * "
tsetup_datain_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
tsetup_dataa_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
tsetup_datab_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
tsetup_datac_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
tsetup_datad_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
tsetup_aload_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
thold_datain_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
thold_dataa_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
thold_datab_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
thold_datac_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
thold_datad_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
thold_aload_clk_noedge_posedge	vitaldelaytype := DefSetupHoldCnst
tpd_clk_regout_posedge	vitaldelaytype01 := DefPropDelay01
tpd_aclr_regout_posedge	vitaldelaytype01 := DefPropDelay01
tpd_clk_qfbko_posedge	vitaldelaytype01 := DefPropDelay01
tpd_aclr_qfbko_posedge	vitaldelaytype01 := DefPropDelay01
tperiod_clk_posedge	vitaldelaytype := DefPulseWdthCnst
tipd_dataa	vitaldelaytype01 := DefPropDelay01
tipd_datab	vitaldelaytype01 := DefPropDelay01
tipd_datac	vitaldelaytype01 := DefPropDelay01
tipd_datad	vitaldelaytype01 := DefPropDelay01
tipd_aclr	vitaldelaytype01 := DefPropDelay01
tipd_aload	vitaldelaytype01 := DefPropDelay01
tipd_clk	vitaldelaytype01 := DefPropDelay01
Ports
clk	in std_logic
datain	in std_logic := ' 1 '
dataa	in std_logic := ' 1 '
datab	in std_logic := ' 1 '
datac	in std_logic := ' 1 '
datad	in std_logic := ' 1 '
aclr	in std_logic := ' 0 '
aload	in std_logic := ' 0 '
devclrn	in std_logic := ' 1 '
devpor	in std_logic := ' 1 '
regout	out std_logic
qfbko	out std_logic
Attributes
VITAL_LEVEL0	TRUE

---

Member Data Documentation

aclr in std_logic := ' 0 ' [Port]

aload in std_logic := ' 0 ' [Port]

atom_pack package [Package]

clk in std_logic [Port]

clock_enable_mode string := " false " [Generic]

dataa in std_logic := ' 1 ' [Port]

datab in std_logic := ' 1 ' [Port]

datac in std_logic := ' 1 ' [Port]

datad in std_logic := ' 1 ' [Port]

datain in std_logic := ' 1 ' [Port]

devclrn in std_logic := ' 1 ' [Port]

devpor in std_logic := ' 1 ' [Port]

IEEE library [Library]

InstancePath string := " * " [Generic]

MsgOn boolean := DefGlitchMsgOn [Generic]

MsgOnChecks boolean := DefMsgOnChecks [Generic]

operation_mode string := " normal " [Generic]

packed_mode string := " false " [Generic]

qfbko out std_logic [Port]

regout out std_logic [Port]

std_logic_1164 package [Package]

thold_aload_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

thold_dataa_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

thold_datab_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

thold_datac_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

thold_datad_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

thold_datain_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

TimingChecksOn boolean := true [Generic]

tipd_aclr vitaldelaytype01 := DefPropDelay01 [Generic]

tipd_aload vitaldelaytype01 := DefPropDelay01 [Generic]

tipd_clk vitaldelaytype01 := DefPropDelay01 [Generic]

tipd_dataa vitaldelaytype01 := DefPropDelay01 [Generic]

tipd_datab vitaldelaytype01 := DefPropDelay01 [Generic]

tipd_datac vitaldelaytype01 := DefPropDelay01 [Generic]

tipd_datad vitaldelaytype01 := DefPropDelay01 [Generic]

tpd_aclr_qfbko_posedge vitaldelaytype01 := DefPropDelay01 [Generic]

tpd_aclr_regout_posedge vitaldelaytype01 := DefPropDelay01 [Generic]

tpd_clk_qfbko_posedge vitaldelaytype01 := DefPropDelay01 [Generic]

tpd_clk_regout_posedge vitaldelaytype01 := DefPropDelay01 [Generic]

tperiod_clk_posedge vitaldelaytype := DefPulseWdthCnst [Generic]

tsetup_aload_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

tsetup_dataa_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

tsetup_datab_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

tsetup_datac_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

tsetup_datad_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

tsetup_datain_clk_noedge_posedge vitaldelaytype := DefSetupHoldCnst [Generic]

VITAL_LEVEL0 TRUE [Attribute]

Reimplemented from vital_le_reg.

VITAL_Primitives package [Package]

VITAL_Timing package [Package]

x_on_violation string := " on " [Generic]

XOn boolean := DefGlitchXOn [Generic]

XOnChecks boolean := DefXOnChecks [Generic]

---

The documentation for this class was generated from the following file:

• flex10ke/flex10ke_atoms.vhd