rtl_direct Architecture Reference

Inheritance diagram for rtl_direct:

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Collaboration diagram for rtl_direct:

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List of all members.

Processes
update_state	( clk , rstb )
addr_fsm	( st_i , sda_in , scl , cnt_8 , en_fec_i , rw_i , finish_tx , finish_rx )
get_addr	( clk , rstb )
Constants
ST_idle	std_logic_vector ( 3 downto 0 ) := " 0000 "
ST_wait_start	std_logic_vector ( 3 downto 0 ) := " 0001 "
ST_start	std_logic_vector ( 3 downto 0 ) := " 0010 "
ST_wait_add	std_logic_vector ( 3 downto 0 ) := " 0011 "
ST_latch_add	std_logic_vector ( 3 downto 0 ) := " 0100 "
ST_fec_add	std_logic_vector ( 3 downto 0 ) := " 0101 "
ST_ack_1	std_logic_vector ( 3 downto 0 ) := " 0110 "
ST_s_rx	std_logic_vector ( 3 downto 0 ) := " 0111 "
ST_s_tx	std_logic_vector ( 3 downto 0 ) := " 1000 "
Types
state_t	( idle , wait_start , start , wait_add , latch_add , fec_add , ack_1 , s_rx , s_tx )
Signals
st_i	state_t := idle
nx_st_i	state_t
addr_i	std_logic_vector ( 4 downto 0 )
rw_i	std_logic := ' 0 '
ready_i	std_logic := ' 0 '
en_fec_i	std_logic := ' 0 '
bcast_i	std_logic := ' 0 '

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Member Function Documentation

[Process]

addr_fsm		( st_i ,
		sda_in ,
		scl ,
		cnt_8 ,
		en_fec_i ,
		rw_i ,
		finish_tx ,
		finish_rx )

[Process]

get_addr		( clk ,
		rstb )

[Process]

update_state		( clk ,
		rstb )

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Member Data Documentation

addr_i std_logic_vector ( 4 downto 0 ) [Signal]

bcast_i std_logic := ' 0 ' [Signal]

en_fec_i std_logic := ' 0 ' [Signal]

nx_st_i state_t [Signal]

ready_i std_logic := ' 0 ' [Signal]

rw_i std_logic := ' 0 ' [Signal]

ST_ack_1 std_logic_vector ( 3 downto 0 ) := " 0110 " [Constant]

ST_fec_add std_logic_vector ( 3 downto 0 ) := " 0101 " [Constant]

st_i state_t := idle [Signal]

ST_idle std_logic_vector ( 3 downto 0 ) := " 0000 " [Constant]

ST_latch_add std_logic_vector ( 3 downto 0 ) := " 0100 " [Constant]

ST_s_rx std_logic_vector ( 3 downto 0 ) := " 0111 " [Constant]

ST_s_tx std_logic_vector ( 3 downto 0 ) := " 1000 " [Constant]

ST_start std_logic_vector ( 3 downto 0 ) := " 0010 " [Constant]

ST_wait_add std_logic_vector ( 3 downto 0 ) := " 0011 " [Constant]

ST_wait_start std_logic_vector ( 3 downto 0 ) := " 0001 " [Constant]

state_t ( idle , wait_start , start , wait_add , latch_add , fec_add , ack_1 , s_rx , s_tx ) [Type]

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The documentation for this class was generated from the following file:

• bc/bc_core/slave/fec_address/fec_address.vhd