rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
fsm	( clk , rstb )
Constants
NDAC	integer := 8
WRITE_LENGTH	integer := 4
NBRANCH	integer := 5
addresses	dac_list := ( 7 = > ( 0 , 0 ) , 6 = > ( 0 , 1 ) , 5 = > ( 0 , 2 ) , 4 = > ( 0 , 3 ) , 3 = > ( 1 , 0 ) , 2 = > ( 1 , 1 ) , 1 = > ( 1 , 2 ) , 0 = > ( 1 , 3 ) )
Types
state_t	( idle , setup , new_dac , write_dac , finish )
dac_list	array ( NDAC -1 downto 0 ) of dac_entry
dac_values	array ( NDAC -1 downto 0 ) of std_logic_vector ( 7 downto 0 )
Signals
values_i	dac_values
state_i	state_t
i	integer range 0 to NDAC +1
j	integer range 0 to WRITE_LENGTH +1
start_i	std_logic
Records
dac_entry : record
dac_id	integer
dac_ch	integer

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Member Function Documentation

[Process]

fsm		( clk ,
		rstb )

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Member Data Documentation

dac_id integer [Record]

dac_ch integer [Record]

addresses dac_list := ( 7 = > ( 0 , 0 ) , 6 = > ( 0 , 1 ) , 5 = > ( 0 , 2 ) , 4 = > ( 0 , 3 ) , 3 = > ( 1 , 0 ) , 2 = > ( 1 , 1 ) , 1 = > ( 1 , 2 ) , 0 = > ( 1 , 3 ) ) [Constant]

dac_entry [Record]

dac_list array ( NDAC -1 downto 0 ) of dac_entry [Type]

dac_values array ( NDAC -1 downto 0 ) of std_logic_vector ( 7 downto 0 ) [Type]

i integer range 0 to NDAC +1 [Signal]

j integer range 0 to WRITE_LENGTH +1 [Signal]

NBRANCH integer := 5 [Constant]

NDAC integer := 8 [Constant]

start_i std_logic [Signal]

state_i state_t [Signal]

state_t ( idle , setup , new_dac , write_dac , finish ) [Type]

values_i dac_values [Signal]

WRITE_LENGTH integer := 4 [Constant]

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The documentation for this class was generated from the following file:

• bc/fmdd/dac_interface/dac_interface.vhd