dac_interface Entity Reference

Inheritance diagram for dac_interface:

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Collaboration diagram for dac_interface:

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List of all members.

Architectures
rtl	Architecture
Libraries
ieee
Packages
std_logic_1164
numeric_std
Generics
DELAYED	boolean := true
Ports
shape_bias_0	in std_logic_vector ( 7 downto 0 )
shape_bias_1	in std_logic_vector ( 7 downto 0 )
vfp_0	in std_logic_vector ( 7 downto 0 )
vfp_1	in std_logic_vector ( 7 downto 0 )
vfs_0	in std_logic_vector ( 7 downto 0 )
vfs_1	in std_logic_vector ( 7 downto 0 )
cal_pulse_lvl	in std_logic_vector ( 7 downto 0 )
test_analog	in std_logic_vector ( 7 downto 0 )
clk	in std_logic
rstb	in std_logic
start	in std_logic
inhibit	in std_logic
busy	out std_logic
dac_addr	out std_logic_vector ( 11 downto 0 )
dac_data	out std_logic_vector ( 7 downto 0 )

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Member Data Documentation

busy out std_logic [Port]

cal_pulse_lvl in std_logic_vector ( 7 downto 0 ) [Port]

clk in std_logic [Port]

dac_addr out std_logic_vector ( 11 downto 0 ) [Port]

dac_data out std_logic_vector ( 7 downto 0 ) [Port]

DELAYED boolean := true [Generic]

ieee library [Library]

inhibit in std_logic [Port]

numeric_std package [Package]

rstb in std_logic [Port]

shape_bias_0 in std_logic_vector ( 7 downto 0 ) [Port]

shape_bias_1 in std_logic_vector ( 7 downto 0 ) [Port]

start in std_logic [Port]

std_logic_1164 package [Package]

test_analog in std_logic_vector ( 7 downto 0 ) [Port]

vfp_0 in std_logic_vector ( 7 downto 0 ) [Port]

vfp_1 in std_logic_vector ( 7 downto 0 ) [Port]

vfs_0 in std_logic_vector ( 7 downto 0 ) [Port]

vfs_1 in std_logic_vector ( 7 downto 0 ) [Port]

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The documentation for this class was generated from the following file:

• bc/fmdd/dac_interface/dac_interface.vhd