rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
fsm	( clk , rstb )
Types
state_t	( idle , setup_strip , setup_pulse , change_pulse , wait_pulse , wait_dac , wait_l2 , done )
Signals
state_i	state_t
	State type State.
l2_cnt_i	integer range 0 to 2 **16
	L2 counter.
strip_cnt_i	integer range 0 to 2 **16
	Strip counter.
max_i	integer range 0 to 2 **8
	Max strip (as integer);.
iter_i	integer range 0 to 2 **16
	Iterations (as integer).
dpulse_i	integer range 0 to 2 **8
	Step size (as integer).
pulse_i	integer range 0 to 2 **8
	Pulse (as integer).
l2_old_i	std_logic

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Member Function Documentation

[Process]

fsm		( clk ,
		rstb )

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Member Data Documentation

dpulse_i integer range 0 to 2 **8 [Signal]

Step size (as integer).

iter_i integer range 0 to 2 **16 [Signal]

Iterations (as integer).

l2_cnt_i integer range 0 to 2 **16 [Signal]

L2 counter.

l2_old_i std_logic [Signal]

max_i integer range 0 to 2 **8 [Signal]

Max strip (as integer);.

pulse_i integer range 0 to 2 **8 [Signal]

Pulse (as integer).

state_i state_t [Signal]

State type State.

state_t ( idle , setup_strip , setup_pulse , change_pulse , wait_pulse , wait_dac , wait_l2 , done ) [Type]

strip_cnt_i integer range 0 to 2 **16 [Signal]

Strip counter.

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The documentation for this class was generated from the following file:

• bc/fmdd/cal_manager/cal_manager.vhd