bc Entity Reference
[Board controller code]
Inheritance diagram for bc:
Collaboration diagram for bc:
Architectures | |
| rtl | Architecture |
Libraries | |
| ieee | |
Packages | |
| std_logic_1164 | |
| numeric_std | |
| bc_core_pack | Package <bc_core_pack> |
| drivers_pack | Package <drivers_pack> |
| altro_sw_mask_in_pack | Package <altro_sw_mask_in_pack> |
| fmdd_pack | Package <fmdd_pack> |
| meb_watchdog_pack | Package <meb_watchdog_pack> |
Ports | |
| clk | in std_logic |
| rstb | in std_logic |
| sclk | in std_logic |
| scl | in std_logic |
| sda_in | in std_logic |
| sda_out | out std_logic |
| l0 | in std_logic |
| l1b | in std_logic |
| l2b | in std_logic |
| mscl | out std_logic |
| msda | inout std_logic |
| pasa_sw | out std_logic |
| paps_errorb | in std_logic |
| rdoclk_en | out std_logic |
| adcclk_en | out std_logic |
| adc_add0 | out std_logic |
| adc_add1 | out std_logic |
| test_a | out std_logic |
| test_b | out std_logic |
| test_c | out std_logic |
| rst_fbc | out std_logic |
| hadd | in std_logic_vector ( 4 downto 0 ) |
| bcout_ad | out std_logic_vector ( 4 downto 0 ) |
| oeba_l | out std_logic |
| oeab_l | out std_logic |
| oeba_h | out std_logic |
| oeab_h | out std_logic |
| ctr_in | out std_logic |
| ctr_out | out std_logic |
| bd | inout std_logic_vector ( 39 downto 0 ) |
| acknb | inout std_logic |
| errorb | inout std_logic |
| trsfb | inout std_logic |
| dstbb | inout std_logic |
| writeb | inout std_logic |
| cstbb | inout std_logic |
| bc_int | out std_logic |
| otib | in std_logic |
| mcst | out std_logic |
| clk10 | in std_logic |
| debug_on | in std_logic |
| altro_sw | out std_logic |
| sample_clk | out std_logic_vector ( 2 downto 0 ) |
| altro_l1 | out std_logic |
| altro_l2 | out std_logic |
| alps_errorb | in std_logic |
| al_dolo_enb | in std_logic |
| al_trsf_enb | in std_logic |
| al_ackn_enb | in std_logic |
| digital_reset | out std_logic |
| test_on | out std_logic |
| pulser_enable | out std_logic |
| shift_in | out std_logic_vector ( 2 downto 0 ) |
| shift_clk | out std_logic_vector ( 2 downto 0 ) |
| hold | out std_logic_vector ( 2 downto 0 ) |
| dac_addr | out std_logic_vector ( 11 downto 0 ) |
| dac_data | out std_logic_vector ( 7 downto 0 ) |
| busy | out std_logic |
| debug | out std_logic_vector ( 14 downto 0 ) |
Detailed Description
Top-level entity of the board controller
Member Data Documentation
acknb inout std_logic [Port] |
adc_add0 out std_logic [Port] |
adc_add1 out std_logic [Port] |
adcclk_en out std_logic [Port] |
al_ackn_enb in std_logic [Port] |
al_dolo_enb in std_logic [Port] |
al_trsf_enb in std_logic [Port] |
alps_errorb in std_logic [Port] |
altro_l1 out std_logic [Port] |
altro_l2 out std_logic [Port] |
altro_sw out std_logic [Port] |
altro_sw_mask_in_pack package [Package] |
bc_core_pack package [Package] |
bc_int out std_logic [Port] |
bcout_ad out std_logic_vector ( 4 downto 0 ) [Port] |
bd inout std_logic_vector ( 39 downto 0 ) [Port] |
busy out std_logic [Port] |
clk in std_logic [Port] |
clk10 in std_logic [Port] |
cstbb inout std_logic [Port] |
ctr_in out std_logic [Port] |
ctr_out out std_logic [Port] |
dac_addr out std_logic_vector ( 11 downto 0 ) [Port] |
dac_data out std_logic_vector ( 7 downto 0 ) [Port] |
debug out std_logic_vector ( 14 downto 0 ) [Port] |
debug_on in std_logic [Port] |
digital_reset out std_logic [Port] |
drivers_pack package [Package] |
dstbb inout std_logic [Port] |
errorb inout std_logic [Port] |
fmdd_pack package [Package] |
hadd in std_logic_vector ( 4 downto 0 ) [Port] |
hold out std_logic_vector ( 2 downto 0 ) [Port] |
ieee library [Library] |
l0 in std_logic [Port] |
l1b in std_logic [Port] |
l2b in std_logic [Port] |
mcst out std_logic [Port] |
meb_watchdog_pack package [Package] |
mscl out std_logic [Port] |
msda inout std_logic [Port] |
numeric_std package [Package] |
oeab_h out std_logic [Port] |
oeab_l out std_logic [Port] |
oeba_h out std_logic [Port] |
oeba_l out std_logic [Port] |
otib in std_logic [Port] |
paps_errorb in std_logic [Port] |
pasa_sw out std_logic [Port] |
pulser_enable out std_logic [Port] |
rdoclk_en out std_logic [Port] |
rst_fbc out std_logic [Port] |
rstb in std_logic [Port] |
sample_clk out std_logic_vector ( 2 downto 0 ) [Port] |
scl in std_logic [Port] |
sclk in std_logic [Port] |
sda_in in std_logic [Port] |
sda_out out std_logic [Port] |
shift_clk out std_logic_vector ( 2 downto 0 ) [Port] |
shift_in out std_logic_vector ( 2 downto 0 ) [Port] |
std_logic_1164 package [Package] |
test_a out std_logic [Port] |
test_b out std_logic [Port] |
test_c out std_logic [Port] |
test_on out std_logic [Port] |
trsfb inout std_logic [Port] |
writeb inout std_logic [Port] |
The documentation for this class was generated from the following file:
- bc/bc.vhd
