altro Entity Reference
[Model of ALTRO chip]

Inheritance diagram for altro:
Inheritance graph
[legend]
Collaboration diagram for altro:
Collaboration graph
[legend]

List of all members.



Architectures

rtl Architecture

Libraries

ieee 
altro_model 
 ALTRO model library.

Packages

std_logic_1164 
numeric_std 
interface_pack  Package <interface_pack>
data_types_pack  Package <data_types_pack>

Generics

HADD  std_logic_vector ( 7 downto 0 ) := " 00000001 "

Ports

clk  in std_logic
clk2  in std_logic
rstb  in std_logic
 Reset.
trg  in std_logic
 trigger
l2y  in std_logic
 L2 accept.
cstb  in std_logic
 Control strobe.
writeb  in std_logic
 write input
ackb  out std_logic
 acknowledge;
ackb_en  out std_logic
 acknowledge enable
dolob_en  out std_logic
 Data output enable.
trsfb  out std_logic
 Transfer gate.
trsfb_en  out std_logic
 Transfer enable.
dstb  out std_logic
 Data strobe.
errorb  out std_logic
 Error.
tstoutb  out std_logic
 Test output.
bd  inout std_logic_vector ( 39 downto 0 )
 Bus.
data  in data_vector
 data

Detailed Description

Model of ALTRO. This is the top-level entity of the model


Member Data Documentation

ackb out std_logic [Port]

acknowledge;

ackb_en out std_logic [Port]

acknowledge enable

altro_model library [Library]

ALTRO model library.

bd inout std_logic_vector ( 39 downto 0 ) [Port]

Bus.

clk in std_logic [Port]
clk2 in std_logic [Port]
cstb in std_logic [Port]

Control strobe.

data in data_vector [Port]

data

data_types_pack package [Package]
dolob_en out std_logic [Port]

Data output enable.

dstb out std_logic [Port]

Data strobe.

errorb out std_logic [Port]

Error.

HADD std_logic_vector ( 7 downto 0 ) := " 00000001 " [Generic]
ieee library [Library]
interface_pack package [Package]
l2y in std_logic [Port]

L2 accept.

numeric_std package [Package]
rstb in std_logic [Port]

Reset.

std_logic_1164 package [Package]
trg in std_logic [Port]

trigger

trsfb out std_logic [Port]

Transfer gate.

trsfb_en out std_logic [Port]

Transfer enable.

tstoutb out std_logic [Port]

Test output.

writeb in std_logic [Port]

write input


The documentation for this class was generated from the following file:
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