ad7417 Entity Reference
[Behavoural Model of AD7417 5-channel 10bit ADC]

Top entity of AD7417 model. More...

Inheritance diagram for ad7417:
Inheritance graph
[legend]
Collaboration diagram for ad7417:
Collaboration graph
[legend]

List of all members.



Architectures

behaviour Architecture
 Architecture of AD7417 model. More...

Libraries

ieee 

Packages

std_logic_1164 
numeric_std 

Generics

VENDOR  std_logic_vector ( 3 downto 0 ) := " 0101 "
 Vendor ID.
ADD  std_logic_vector ( 2 downto 0 ) := " 000 "
 Address.
PERIOD  time := 6.6 us
 Period of clk.
T  unsigned ( 15 downto 0 ) := x " dead "
 T value.
ADC1  unsigned ( 15 downto 0 ) := x " beaf "
 ADC1 value.
ADC2  unsigned ( 15 downto 0 ) := x " 1111 "
 ADC2 value.
ADC3  unsigned ( 15 downto 0 ) := x " 0000 "
 ADC3 value.
ADC4  unsigned ( 15 downto 0 ) := x " aaaa "
 ADC4 value.

Ports

scl  inout std_logic
 I2C Clock.
sda  inout std_logic
 I2C data.

Detailed Description

Top entity of AD7417 model.


Member Data Documentation

ADC1 unsigned ( 15 downto 0 ) := x " beaf " [Generic]

ADC1 value.

ADC2 unsigned ( 15 downto 0 ) := x " 1111 " [Generic]

ADC2 value.

ADC3 unsigned ( 15 downto 0 ) := x " 0000 " [Generic]

ADC3 value.

ADC4 unsigned ( 15 downto 0 ) := x " aaaa " [Generic]

ADC4 value.

ADD std_logic_vector ( 2 downto 0 ) := " 000 " [Generic]

Address.

ieee library [Library]
numeric_std package [Package]
PERIOD time := 6.6 us [Generic]

Period of clk.

scl inout std_logic [Port]

I2C Clock.

sda inout std_logic [Port]

I2C data.

std_logic_1164 package [Package]
T unsigned ( 15 downto 0 ) := x " dead " [Generic]

T value.

VENDOR std_logic_vector ( 3 downto 0 ) := " 0101 " [Generic]

Vendor ID.


The documentation for this class was generated from the following file:
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