Registers
[Board controller code]

Collaboration diagram for Registers:

Architectures

register_config Package

Detailed Description

Registers and commands

The register table is as follows:

Name Addr BCast I2C Access Default Width Description
Monitors
t1_th 0x01 X X rw 0x00A0 10 First ADC Temperature threshold
flash_i_th 0x02 X X rw 0x03FF 10 Flash current threshold
al_dig_i_th 0x03 X X rw 0x03FF 10 ALTRO digital current threshold
al_ana_i_th 0x04 X X rw 0x03FF 10 ALTRO analog current threshold
va_rec_ip_th 0x05 X X rw 0x03FF 10 VA positive rec. cur. threshold
t1 0x06   X r 0x00A0 10 First ADC Temperature
flash_i 0x07   X r 0x03ff 10 Flash current
al_dig_i 0x08   X r 0x03ff 10 ALTRO digitial current
al_ana_i 0x09   X r 0x03ff 10 ALTRO analog current
va_rec_ip 0x0A   X r 0x03ff 10 VA positive rec. current
t2_th 0x2D X X rw 0x00A0 10 Second ADC Temperature threhold
va_sup_ip_th 0x2E X X rw 0x03FF 10 VA positive sup. cur. threshold
va_rec_im_th 0x2F X X rw 0x03FF 10 VA negative rec. cur. threshold
va_sup_im_th 0x30 X X rw 0x03FF 10 VA negative sup. cur. threshold
gtl_u_th 0x31 X X rw 0x0000 10 Digital driver voltage threshold
t2 0x32   X r 0x00A0 10 Second ADC Temperature
va_sup_ip 0x33   X r 0x03ff 10 VA positive sup. cur.
va_rec_im 0x34   X r 0x03ff 10 VA negative rec. cur.
va_sup_im 0x35   X r 0x03ff 10 VA negative sup. cur.
gtl_u 0x36   X r 0x03ff 10 Digital driver voltage
t3_th 0x37 X X rw 0x00A0 10 Third ADC Temperature threshold
t1sens_th 0x38 X X rw 0x01FF 10 Temperature sens. 1 threshold
t2sens_th 0x39 X X rw 0x01FF 10 Temperature sens. 2 threshold
al_dig_u_th 0x3A X X rw 0x0000 10 ALTRO digital voltage threshold
al_ana_u_th 0x3B X X rw 0x0000 10 ALTRO analog voltage threshold
t3 0x3C   X r 0x00A0 10 Third ADC Temperature
t1sens 0x3D   X r 0x01FF 10 Temperature sens. 1
t2sens 0x3E   X r 0x01FF 10 Temperature sens. 2
al_dig_u 0x3F   X r 0x0000 10 ALTRO digital voltage
al_ana_u 0x40   X r 0x0000 10 ALTRO analog voltage
t4_th 0x41 X X rw 0x00A0 10 Forth ADC Temperature threshold
va_rec_up_th 0x42 X X rw 0x0000 10 VA positive rec. voltage threshold
va_sup_up_th 0x43 X X rw 0x0000 10 VA positive sup. voltage threshold
va_sup_um_th 0x44 X X rw 0x03FF 10 VA negative sup. voltage threshold
va_rec_um_th 0x45 X X rw 0x03FF 10 VA negative rec. voltage threshold
t4 0x46   X r 0x00A0 10 Forth ADC Temperature
va_rec_up 0x47   X r 0x0000 10 VA positive rec. voltage
va_sup_up 0x48   X r 0x0000 10 VA positive sup. voltage
va_sup_um 0x49   X r 0x03FF 10 VA negative sup. voltage
va_rec_um 0x4A   X r 0x03FF 10 VA negative rec. voltage
Counters
l1cnt 0x0B   X r 0x0000 16 L1 trigger CouNTer
l2cnt 0x0C   X r 0x0000 16 L2 trigger CouNTer
sclkcnt 0x0D   X r 0x0000 16 Sampling CLK CouNTer
dstbcnt 0x0E   X r 0x0000 16 DSTB CouNTer
Test mode
tsm_word 0x0F X X rw 0x0001 9 Test mode word
us_ratio 0x10 X X rw 0x0001 16 Undersampling ratio.
Configuration and status
csr0 0x11 X X rw 0x07FF 11 Config/Status Reg. 0
csr1 0x12 X X rw 0x0000 14 Config/Status Reg. 1
csr2 0x13 X X rw 0x000F 16 Config/Status Reg. 2
csr3 0x14 X X rw 0x2220 16 Config/Status Reg. 3
free 0x15 X X rw 0x0000 0 Free
Comands:
cntlat 0x16 X X rw 0x0000 0 Latch counters
cntclr 0x17 X X rw 0x0000 0 Clear counters
csr1clr 0x18 X X rw 0x0000 0 Clear CSR1
alrst 0x19 X X rw 0x0000 0 rstb ALTROs
bcrst 0x1A X X rw 0x0000 0 rstb BC
stcnv 0x1B X X rw 0x0000 0 Start conversion
scevl 0x1C X   rw 0x0000 0 Scan event length
evlrdo 0x1D X   rw 0x0000 0 Read event length
sttsm 0x1E X   rw 0x0000 0 Start test mode
acqrdo 0x1F X   rw 0x0000 0 Read acq. memory
FMD
fmdd_stat 0x20 X   r 0x0000 16 FMDD status
l0cnt 0x21 X   r 0x0000 16 L0 counters
hold_wait 0x22 X   rw 0x0020 16 Wait to hold
l1_timeout 0x23 X   rw 0x00F0 16 L1 timeout
l2_timeout 0x24 X   rw 0x0E00 16 L2 timeout
shift_div 0x25 X   rw 0x1000 16 Shift clk
strips 0x26 X   rw 0x7F00 16 Strips
cal_level 0x27 X   rw 0x2000 16 Cal pulse
shape_bias 0x28 X   rw 0x2A20 16 Shape bias
vfs 0x29 X   rw 0x645D 16 Shape ref
vfp 0x2A X   rw 0x878B 16 Preamp ref
sample_div 0x2B X   rw 0x0402 16 Sample clk
fmdd_cmd 0x2C X   rw 0x0000 16 Commands
cal_iter 0x4B X   rw 0x0064 16 Cal events
mebs 0x4C X   rw 0x0144 9 Multi-event config

Monitor registers

The monitor registers fall in two groups: the threshold and the current ADC value. The current values are read-only, while the thresholds can be read and written. The conversion factors and offsets, as well as the units are given below. Note, that only current value is described. The parameters are the same for the thresholds.

NameOffsetFactorUnitNotes
t1 00.25C 
flash_i 01mA3.3 V
al_dig_i 01mA2.5 V
al_ana_i 01mA2.5 V
va_rec_ip 01mA2.5 V
t2 00.25C 
va_sup_ip 01mA1.5 V
va_rec_im 01mA-2.0 V
va_sup_im 01mA-2.0 V
gtl_u 03.3/512V2.5 V
t3 00.25C 
t1sens 00.10C 
t2sens 00.10C 
al_dig_u 02.5/512V2.5 V
al_ana_u 02.5/512V2.5 V
t4 00.25C 
va_rec_up 02.5/512V2.5 V
va_sup_up 01.5/512V1.5 V
va_sup_um 04.5/512V-2.0 V
va_rec_um 04.5/512V-2.0 V

The current values are continously updated if continous conversion is enabled in CSR0. Otherwise, a single conversion can be initiated via the command STCNV.

The monitor values are mapped as follows to the 5 interrupt lines

al_dig_idigital over-current
flash_i
va_rec_ip
al_dig_udigital under-voltage
gtl_u
va_rec_up
al_ana_ianalog over-current
va_sup_ip
va_rec_im
va_sup_im
al_ana_uanalog under-voltage
va_sup_up
va_rec_um
va_sup_um
t1over-temperature
t2
t3
t4
t1sens
t2sens

Counters

The BC contains a number of counters for diagnostics. It will count the number of triggers (L0, L1, and L2) as well as the number of last seen data strobes (40bit words transmitted by ALTROs), and possible missed sample clocks.

The current values of the counters is stored in registers by issuing the command CNTLAT. By sending this command in broadcast, one can compare number of triggers received over all front-end cards.

The counters are clear by the command CNTCLR.

Test mode

Test mode is disabled in the FMD digitiser BC firmware, and these registers have no meaning. They are kept only for backward compatibility.

Configuration and status registers

The main operational parameters of the BC are the 4 configuration and status registers CSR0, CSR1, CSR2, and CSR3.

Configuration and status register 0

This register holds the interrupt and error mask of the BC. The register is segmented as follows:

BitDescription
10Enable continous conversion
9Enable BC instruction errors
8Enable parity errors
7Enable missed sample clock interrupt
6Enable ALTRO power supply interrupt
5Enable PASA power supply interrupt
4Enable digital over-current interrupt
3Enable digital under-voltage interrupt
2Enable analog over-current interrupt
1Enable analog under-voltage interrupt
0Enable over-temperature interrupt
Configuration and status 1

This register holds the current status of the BC. The errors and interrupts of this register can be masked out by setting the corresponding bit of CSR0 to '0'. This register is read-only.

BitDescription
13Interrupt (OR of 8 interrupt lines)
12Error (OR of 4 interrupt lines)
11I2C bus error
10ALTRO error
9BC instruction errors
9BC instruction errors
8Parity errors
7Missed sample clock interrupt
6ALTRO power supply interrupt
5PASA power supply interrupt
4Digital over-current interrupt
3Digital under-voltage interrupt
2Analog over-current interrupt
1Analog under-voltage interrupt
0Over-temperature interrupt
Configuration and status 2

This holds the hardware address, test-mode parameters, and enables/.

Bit(s)Description
15-11Hardware address
10Card isolated
9Continous test mode
8- 6ALTRO address
5- 4Channel address
3Sample clock enable
2Readout clock enable
1PASA switch
0ALTRO switch

Test mode is disabled in the FMD BC firmware, so bits 10-4 are meaningless. Bit 0 is connected to the enable of the power regulator of both the ALTRO and BC, so this bit <emph>must</emph> always be asserted.

Configuration and status register 3
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