Architectures | |
rtl2 | Architecture |
Libraries | |
ieee | |
Packages | |
std_logic_1164 | |
numeric_std | |
Ports | |
clk | in std_logic |
Clock. | |
rstb | in std_logic |
Async reset. | |
l0 | in std_logic |
Level 0 Trigger (active high). | |
l1 | in std_logic |
Level 1 trigger (active low). | |
l2 | in std_logic |
Level 2 trigger (active low). | |
l2r | in std_logic |
L2 reject (timeout). | |
l1r | in std_logic |
L1 reject (timeout). | |
hold | out std_logic |
Hold to VA1s. | |
busy | out std_logic |
Busy to CTP. | |
hold_wait | in std_logic_vector ( 15 downto 0 ) |
Wait to hold. | |
cal_delay | in std_logic_vector ( 15 downto 0 ) |
Extra delay (cal). | |
sequencer_start | out std_logic |
Start sequencer. | |
sequencer_busy | in std_logic |
Sequencer is busy. | |
sequencer_clear | out std_logic |
Clear sequencer. | |
cal_on | in std_logic |
Calibration mode. | |
pulser_enable | out std_logic |
Step pulser single - active low. | |
incomplete | out std_logic |
Status word. |
busy out std_logic [Port] |
Busy to CTP.
cal_delay in std_logic_vector ( 15 downto 0 ) [Port] |
Extra delay (cal).
cal_on in std_logic [Port] |
Calibration mode.
clk in std_logic [Port] |
Clock.
hold out std_logic [Port] |
Hold to VA1s.
hold_wait in std_logic_vector ( 15 downto 0 ) [Port] |
Wait to hold.
ieee library [Library] |
incomplete out std_logic [Port] |
Status word.
l0 in std_logic [Port] |
Level 0 Trigger (active high).
l1 in std_logic [Port] |
Level 1 trigger (active low).
l1r in std_logic [Port] |
L1 reject (timeout).
l2 in std_logic [Port] |
Level 2 trigger (active low).
l2r in std_logic [Port] |
L2 reject (timeout).
numeric_std package [Package] |
pulser_enable out std_logic [Port] |
Step pulser single - active low.
rstb in std_logic [Port] |
Async reset.
sequencer_busy in std_logic [Port] |
Sequencer is busy.
sequencer_clear out std_logic [Port] |
Clear sequencer.
sequencer_start out std_logic [Port] |
Start sequencer.
std_logic_1164 package [Package] |