rtl Architecture Reference
Inheritance diagram for rtl:
Collaboration diagram for rtl:
Processes | |
| shift_it | ( clk , rstb ) |
| counter | ( clk , rstb ) |
Signals | |
| cnt_i | std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' ) |
Component Instantiations | |
| got_it | cnt8 <Entity cnt8> |
Member Function Documentation
| counter | ( clk , | |
| rstb ) |
| shift_it | ( clk , | |
| rstb ) |
Member Data Documentation
cnt_i std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' ) [Signal] |
The documentation for this class was generated from the following file:
- bc/bc_core/interface_adc/master/serializer/serializer.vhd
