rtl Architecture Reference
Inheritance diagram for rtl:
Collaboration diagram for rtl:
Processes | |
| sclk_edge | ( rclk , rstb ) |
| clk_count | ( rclk , rstb ) |
| sclk_count | ( sclk , rstb ) |
Signals | |
| clk_counter_i | unsigned ( 7 downto 0 ) |
| sclk_counter_i | unsigned ( 15 downto 0 ) |
| maxed_i | std_logic |
| sclk_clr_i | std_logic |
| sclk_reg_i | std_logic |
| sclk_reg_ii | std_logic |
| sclk_edge_i | std_logic |
Member Function Documentation
| clk_count | ( rclk , | |
| rstb ) |
| sclk_count | ( sclk , | |
| rstb ) |
| sclk_edge | ( rclk , | |
| rstb ) |
Member Data Documentation
clk_counter_i unsigned ( 7 downto 0 ) [Signal] |
maxed_i std_logic [Signal] |
sclk_clr_i std_logic [Signal] |
sclk_counter_i unsigned ( 15 downto 0 ) [Signal] |
sclk_edge_i std_logic [Signal] |
sclk_reg_i std_logic [Signal] |
sclk_reg_ii std_logic [Signal] |
The documentation for this class was generated from the following file:
- bc/bc_core/registers/counters/sclk_counter/sclk_counter.vhd
