test2 Architecture Reference

Inheritance diagram for test2:

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Collaboration diagram for test2:

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List of all members.

Functions
string	slv2str ( constant v: in std_logic_vector )
	Convert std_logic_vector to a string.
Processes
inputs	( scl , start_i )
nwords	( scl , start_i )
start_condition	( sda_in , scl )
stop_condition	( sda_in , scl )
count_scl	( scl , start_i , stop_i )
buffer_data	( start_i , stop_i , scl )
out_data	( cnt_i )
update_state	( scl , stop_i )
fsm	( start_i , stop_i , st_i , cnt_i )
Procedures
	one_out( signal sda_out: out std_logic signal cnt: in integer signal sub: in integer signal data: in std_logic_vector ( 15 downto 0 ) )
Types
st_t	( idle , who , addressed , ack , write_data , read_data , ack_master )
Signals
start_i	boolean := false
stop_i	boolean := false
cnt_i	integer := 0
buffer_i	std_logic_vector ( 7 downto 0 )
rw_i	boolean
sub_i	integer
no_ack_i	boolean
words_i	integer := 0
first_i	boolean
sda_in_i	std_logic
fec_i	std_logic_vector ( 3 downto 0 )
bcast_i	boolean
reg_add_i	std_logic_vector ( 7 downto 0 )
data_i	std_logic_vector ( 7 downto 0 )
st_i	st_t
nx_st_i	st_t

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Member Function Documentation

[Process]

buffer_data		( start_i ,
		stop_i ,
		scl )

[Process]

count_scl		( scl ,
		start_i ,
		stop_i )

[Process]

fsm		( start_i ,
		stop_i ,
		st_i ,
		cnt_i )

[Process]

inputs		( scl ,
		start_i )

[Process]

nwords		( scl ,
		start_i )

[Procedure]

one_out		(signal sda_out out std_logic ,
		signal cnt in integer ,
		signal sub in integer ,
		signal data in std_logic_vector(15 downto 0) )

[Process]

out_data

( cnt_i )

[Function]

string slv2str

(constant v in std_logic_vector )

Convert std_logic_vector to a string.

Parameters:

v

The vector to convert

Returns:

String representation of v

[Process]

start_condition		( sda_in ,
		scl )

[Process]

stop_condition		( sda_in ,
		scl )

[Process]

update_state		( scl ,
		stop_i )

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Member Data Documentation

bcast_i boolean [Signal]

buffer_i std_logic_vector ( 7 downto 0 ) [Signal]

cnt_i integer := 0 [Signal]

data_i std_logic_vector ( 7 downto 0 ) [Signal]

fec_i std_logic_vector ( 3 downto 0 ) [Signal]

first_i boolean [Signal]

no_ack_i boolean [Signal]

nx_st_i st_t [Signal]

reg_add_i std_logic_vector ( 7 downto 0 ) [Signal]

rw_i boolean [Signal]

sda_in_i std_logic [Signal]

st_i st_t [Signal]

st_t ( idle , who , addressed , ack , write_data , read_data , ack_master ) [Type]

start_i boolean := false [Signal]

stop_i boolean := false [Signal]

sub_i integer [Signal]

words_i integer := 0 [Signal]

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The documentation for this class was generated from the following file:

• msmodule/msm_slave.vhd