rtl Architecture Reference
Inheritance diagram for rtl:
Collaboration diagram for rtl:
Processes | |
| counter_proc | ( clk , rstb ) |
| shift_register | ( clk , rstb ) |
Signals | |
| shiftreg_i | std_logic_vector ( 7 downto 0 ) |
| counter_i | unsigned ( 3 downto 0 ) |
Member Function Documentation
| counter_proc | ( clk , | |
| rstb ) |
| shift_register | ( clk , | |
| rstb ) |
Member Data Documentation
counter_i unsigned ( 3 downto 0 ) [Signal] |
shiftreg_i std_logic_vector ( 7 downto 0 ) [Signal] |
The documentation for this class was generated from the following file:
- msmodule/msm_lsc_core/msm_master/msm_serializer_rcu/msm_serializer_rcu.vhd
