rtl Architecture Reference
Inheritance diagram for rtl:
Collaboration diagram for rtl:
Processes | |
| next_state | ( clk , rstb ) |
| fsm | ( st_i , start , stop , cnt_8 , read , write , new_data , cnt_tx_i , error_i ) |
| errors | ( clk , rstb ) |
| recieve_counter | ( clk , rstb , start ) |
| transmit_counter | ( clk , rstb ) |
| output | ( clk , rstb ) |
Constants | |
| sel_master | std_logic_vector ( 1 downto 0 ) := " 00 " |
| sel_ser | std_logic_vector ( 1 downto 0 ) := " 01 " |
| sel_slave | std_logic_vector ( 1 downto 0 ) := " 10 " |
Types | |
| st_t | ( idle , start_1 , start_2 , latch_1 , latch_2 , latch_3 , latch_4 , ack_1 , ack_2 , ack_3 , stop_1 , stop_2 , stop_3 , latch_data_1 , latch_data_2 , latch_data_3 , latch_data_4 , ack_m_1 , ack_m_2 , ack_m_3 , ack_m_4 , n_ack_m_2 , n_ack_m_3 , n_ack_m_4 , nack_1 , nack_2 , nack_3 , wait_new_data ) |
Signals | |
| st_i | st_t := idle |
| nx_st_i | st_t := idle |
| en_cnt_rx_i | std_logic |
| cnt_rx_i | unsigned ( 0 downto 0 ) |
| en_cnt_tx_i | std_logic |
| cnt_tx_i | unsigned ( 1 downto 0 ) |
| error_i | std_logic |
| sel_sda_i | std_logic_vector ( 1 downto 0 ) |
| sda_master_i | std_logic |
| scl_i | std_logic |
Member Function Documentation
| errors | ( clk , | |
| rstb ) |
| fsm | ( st_i , | |
| start , | ||
| stop , | ||
| cnt_8 , | ||
| read , | ||
| write , | ||
| new_data , | ||
| cnt_tx_i , | ||
| error_i ) |
| next_state | ( clk , | |
| rstb ) |
| output | ( clk , | |
| rstb ) |
| recieve_counter | ( clk , | |
| rstb , | ||
| start ) |
| transmit_counter | ( clk , | |
| rstb ) |
Member Data Documentation
cnt_rx_i unsigned ( 0 downto 0 ) [Signal] |
cnt_tx_i unsigned ( 1 downto 0 ) [Signal] |
en_cnt_rx_i std_logic [Signal] |
en_cnt_tx_i std_logic [Signal] |
error_i std_logic [Signal] |
scl_i std_logic [Signal] |
sda_master_i std_logic [Signal] |
sel_master std_logic_vector ( 1 downto 0 ) := " 00 " [Constant] |
sel_sda_i std_logic_vector ( 1 downto 0 ) [Signal] |
sel_ser std_logic_vector ( 1 downto 0 ) := " 01 " [Constant] |
sel_slave std_logic_vector ( 1 downto 0 ) := " 10 " [Constant] |
st_t ( idle , start_1 , start_2 , latch_1 , latch_2 , latch_3 , latch_4 , ack_1 , ack_2 , ack_3 , stop_1 , stop_2 , stop_3 , latch_data_1 , latch_data_2 , latch_data_3 , latch_data_4 , ack_m_1 , ack_m_2 , ack_m_3 , ack_m_4 , n_ack_m_2 , n_ack_m_3 , n_ack_m_4 , nack_1 , nack_2 , nack_3 , wait_new_data ) [Type] |
The documentation for this class was generated from the following file:
- msmodule/msm_lsc_core/msm_master/msm_master_sm/msm_master_sm.vhd
