rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
next_state	( clk , rstb )
fsm	( st_i , read_al , active_card_i , stop , error , last_card_i )
counter	( clk , rstb )
Types
st_t	( s0 , s1 , s2 , s3 , s4 )
Signals
st_i	st_t
nx_st_i	st_t
last_card_i	std_logic
enable_cnt_i	std_logic := ' 0 '
reset_card_i	std_logic
branch_i	std_logic
al_i	std_logic_vector ( 12 downto 0 )
cnt_i	unsigned ( 3 downto 0 ) := X " 0 "
cnt_ii	std_logic_vector ( 3 downto 0 )
active_card_i	std_logic
idx_i	integer := 0
Component Instantiations
branch_selector_1	msm_branch_selector <Entity msm_branch_selector>

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Member Function Documentation

[Process]

counter		( clk ,
		rstb )

[Process]

fsm		( st_i ,
		read_al ,
		active_card_i ,
		stop ,
		error ,
		last_card_i )

[Process]

next_state		( clk ,
		rstb )

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Member Data Documentation

active_card_i std_logic [Signal]

al_i std_logic_vector ( 12 downto 0 ) [Signal]

branch_i std_logic [Signal]

branch_selector_1 msm_branch_selector [Component Instantiation]

cnt_i unsigned ( 3 downto 0 ) := X " 0 " [Signal]

cnt_ii std_logic_vector ( 3 downto 0 ) [Signal]

enable_cnt_i std_logic := ' 0 ' [Signal]

idx_i integer := 0 [Signal]

last_card_i std_logic [Signal]

nx_st_i st_t [Signal]

reset_card_i std_logic [Signal]

st_i st_t [Signal]

st_t ( s0 , s1 , s2 , s3 , s4 ) [Type]

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The documentation for this class was generated from the following file:

• msmodule/msm_lsc_core/msm_interrupt_driver/msm_cards_status/msm_cards_status.vhd