rtl Architecture Reference

Inheritance diagram for rtl:

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Collaboration diagram for rtl:

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List of all members.

Processes
SHIFT_REGISTER	( CLK , rst , SE , DIN , LD )
Signals
pre_Q	std_logic_vector ( ( reg_width -1 ) downto 0 ) := ( others = > ' 0 ' )

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Member Function Documentation

[Process]

SHIFT_REGISTER		( CLK ,
		rst ,
		SE ,
		DIN ,
		LD )

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Member Data Documentation

pre_Q std_logic_vector ( ( reg_width -1 ) downto 0 ) := ( others = > ' 0 ' ) [Signal]

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The documentation for this class was generated from the following file:

• msmodule2/msm2_interface_i2c/msm2_reg_so_bc/msm2_reg_so_bc.vhd