Architectures | |
ARCH_mux_dec | Architecture |
Libraries | |
IEEE | |
Packages | |
STD_LOGIC_1164 | |
Ports | |
sel_sda_out | in std_logic_vector ( 2 downto 0 ) |
sda_out_fsm | in std_logic |
sda_fec_add | in std_logic |
sda_reg_add | in std_logic |
sda_dat_B1 | in std_logic |
sda_dat_B2 | in std_logic |
sel_fec_add | out std_logic |
sel_reg_add | out std_logic |
sel_dat_B1 | out std_logic |
sel_dat_B2 | out std_logic |
sda_out | out std_logic |
IEEE library [Library] |
sda_dat_B1 in std_logic [Port] |
sda_dat_B2 in std_logic [Port] |
sda_fec_add in std_logic [Port] |
sda_out out std_logic [Port] |
sda_out_fsm in std_logic [Port] |
sda_reg_add in std_logic [Port] |
sel_dat_B1 out std_logic [Port] |
sel_dat_B2 out std_logic [Port] |
sel_fec_add out std_logic [Port] |
sel_reg_add out std_logic [Port] |
sel_sda_out in std_logic_vector ( 2 downto 0 ) [Port] |
STD_LOGIC_1164 package [Package] |