

Architectures | |
| ARCH_fsm_i2c | Architecture |
Libraries | |
| IEEE | |
Packages | |
| STD_LOGIC_1164 | |
Ports | |
| rst | in std_logic |
| clk | in std_logic |
| exec | in std_logic |
| rd_nwr | in std_logic |
| sda_in | in std_logic |
| bit_cnt_ovr | in std_logic |
| sclK | out std_logic |
| sel_sda_out | out std_logic_vector ( 2 downto 0 ) |
| sda_out_fsm | out std_logic |
| sv_data_b1 | out std_logic |
| sv_data_b2 | out std_logic |
| en_fec_reg | out std_logic |
| en_bc_reg | out std_logic |
| en_B1_dout | out std_logic |
| en_B2_dout | out std_logic |
| en_cnt_in | out std_logic |
| cnt_in_ovr | in std_logic |
| err_fec_ack | out std_logic |
| err_bc_add | out std_logic |
| err_din1_ack | out std_logic |
| err_din2_ack | out std_logic |
| sv_rslt | out std_logic |
| I2C_BSY | out std_logic |
| end_rd | out std_logic |
| fsm_state | out std_logic_vector ( 7 downto 0 ) |
| en_bit_cnt | out std_logic |
| clr_bit_cnt | out std_logic |
bit_cnt_ovr in std_logic [Port] |
clk in std_logic [Port] |
clr_bit_cnt out std_logic [Port] |
cnt_in_ovr in std_logic [Port] |
en_B1_dout out std_logic [Port] |
en_B2_dout out std_logic [Port] |
en_bc_reg out std_logic [Port] |
en_bit_cnt out std_logic [Port] |
en_cnt_in out std_logic [Port] |
en_fec_reg out std_logic [Port] |
end_rd out std_logic [Port] |
err_bc_add out std_logic [Port] |
err_din1_ack out std_logic [Port] |
err_din2_ack out std_logic [Port] |
err_fec_ack out std_logic [Port] |
exec in std_logic [Port] |
fsm_state out std_logic_vector ( 7 downto 0 ) [Port] |
I2C_BSY out std_logic [Port] |
IEEE library [Library] |
rd_nwr in std_logic [Port] |
rst in std_logic [Port] |
sclK out std_logic [Port] |
sda_in in std_logic [Port] |
sda_out_fsm out std_logic [Port] |
sel_sda_out out std_logic_vector ( 2 downto 0 ) [Port] |
STD_LOGIC_1164 package [Package] |
sv_data_b1 out std_logic [Port] |
sv_data_b2 out std_logic [Port] |
sv_rslt out std_logic [Port] |
1.6.2-20100208